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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? 16,384-channel x 16,384-channel non-blocking unidirectional switching.the backplane and local inputs and outputs can be combined to form a non-blocking switching matrix with 64 input streams and 64 output streams ? 8,192-channel x 8,192-channel non-blocking backplane input to local output stream switch ? 8,192-channel x 8,192-channel non-blocking local input to backplane output stream switch ? 8,192-channel x 8,192-channel non-blocking backplane input to backplane output switch ? 8,192-channel x 8,192-channel non-blocking local input to local output stream switch ? rate conversion on all data paths, backplane-to- local, local-to-backplane, backplane-to- backplane and local-to-local streams ? backplane port accepts 32 input and 32 output st-bus streams with data rates of 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps in any combination, or a fixed allocation of 16 input and 16 output streams at 32.768mbps ? local port accepts 32 input and 32 output st- bus streams with data rates of 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps in any combination, or a fixed allocation of 16 input and 16 output streams at 32.768mbps ? exceptional input clock jitter tolerance (17ns for 16mbps or lower data rates, 14ns for 32mbps) ? per-stream channel and bit delay for local and backplane input streams ? per-stream advancement for local and backplane output streams ? constant 2-frame throughput delay for frame integrity ? per-channel high impedance output control for local and backplane streams ? per-channel driven-high output control for local and backplane streams november 2003 ordering information zl50060gac 256-ball pbga ZL50061gac 272-ball pbga -40 c to +85 c zl50060/1 16k-channel digital switch with high jitter tolerance, per stream rate conversion (2, 4, 8, 16, or 32mbps), and 64 inputs and 64 outputs data sheet figure 1 - zl50060/1 functional block diagram backplane data memories (8,192 channels) ds cs r/w a14-0 dta d15-0 test port microprocessor interface and internal registers v ss (gnd) v dd_core tdi tdo tck trst tms lsto0-31 (8,192 locations) reset local interface connection memory bsti0-31 input timing unit fp8i pll lsti0-31 interface backplane bsto0-31 local c8i v dd_io lcst0-3 ode bcst0-3 c8o c16o fp8o fp16o v dd_pll output timing unit (8,192 locations) connection memory backplane interface local local data memories (8,192 channels) bors lors
zl50060/1 data sheet 2 zarlink semiconductor inc. ? high impedance control outputs for external drivers on local and backplane ports ? per-channel message mode for local and backplane output streams ? connection memory block programming for fast device initialization ? ber testing for local and backplane ports ? automatic selection between st-bus and gci-bus operation ? non-multiplexed motorola microprocessor interface ? conforms to the mandatory requirements of the ieee-1149.1 (jtag) standard ? memory built-in-self-test (bist), controlled via microprocessor register ? 1.8v core supply voltage ? 3.3v i/o supply voltage ? 5v tolerant inputs, outputs and i/os ? ZL50061 is pin-to-pin compatible with zarlink?s mt90869 device 1 note 1: for software compatibility between ZL50061 and mt90869, please refer to section 2.6. applications ? central office switches (class 5) ? media gateways ? class-independent switches ? access concentrators ? scalable tdm-based architectures ? digital loop carriers
zl50060/1 data sheet 3 zarlink semiconductor inc. device overview the zl50060 and ZL50061 are two different packages of the same device. the zl50060/1 has two data ports, the backplane and the local port. both the backplane and local ports have two independent modes of operation, either 32 input and 32 output streams operated at 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps, in any combination, or 16 input and 16 output streams operated at 32.768mbps. the zl50060/1 contains two data memory blocks (backplane and local) to provide the following switching path configurations: ? input-to-output unidirectional, supporting 16k x 16k switching ? backplane-to-local bi-directional, supporting 8k x 8k data switching, ? local-to-backplane bi-directional, supporting 8k x 8k data switching, ? backplane-to-backplane bi-directional, supporting 8k x 8k data switching. ? local-to-local bi-directional, supporting 8k x 8k data switching. the device contains two connection memory blocks, one for the backplane output and one for the local output. data to be output on the serial streams may come from either of the data memories (connection mode) or directly from the connection memory contents (message mode). in connection mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. in message mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per channel basis. this feature is useful for transferring control and status information to external circuits or other st-bus devices. the device uses a master frame pulse (fp8i ) and master clock (c8i ) to define the input frame boundary and timing for both the backplane port and the local port. the device will automatically detect whether an st-bus or a gci- bus style frame pulse is being used. there is a two-frame delay from the time reset is de-asserted to the establishment of full switch functionality. during this period, the input frame pulse format is determined before switching begins. the device provides fp8o , fp16o , c8o and c16o outputs to support external devices connected to the outputs of the backplane and local ports. a non-multiplexed motorola microprocessor port allows programming of the various device operation modes and switching configurations. the microprocessor port provides access for register read/write, connection memory read/write and data memory read-only operations. the port has a 15-bit address bus, 16-bit data bus and 4 control signals. the microprocessor may monitor channel data in the backplane and local data memories. the mandatory requirements of the ieee-1149.1 (jtag) standard are fully supported via a dedicated test port. the zl50060 and ZL50061 are each available in one package: ? zl50060: a 17mm x 17mm body, 1mm ball-pitch, 256-pbga. ? ZL50061: a 27mm x 27mm body, 1.27mm ball-pitch, 272-pbga.
zl50060/1 data sheet table of contents 4 zarlink semiconductor inc. 1.0 unidirectional and bi-directional switching applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1 flexible configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.1.1 non-blocking unidirectional configuration (typical system configuration) . . . . . . . . . . . . . . . . . . 22 1.1.2 non-blocking bi-directional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.1.3 blocking bi-directional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1 switching configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.1 unidirectional switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.2 backplane-to-local path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.3 local-to-backplane path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.4 backplane-to-backplane path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.5 local-to-local path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.6 port data rate modes and selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.7 local port rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1.7.1 local input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1.7.2 local output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.8 backplane port rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.8.1 backplane input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1.8.2 backplane output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 frame pulse input and master input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 input frame pulse and generated frame pulse alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4 jitter tolerance improvement circuit - frame boundary discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 input clock jitter tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6 backward compatibility with mt90869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.0 input and output offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1 input offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.1 input channel delay programming (backplane and local input streams) . . . . . . . . . . . . . . . . . . . 30 3.1.2 input bit delay programming (backplane and local input streams) . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 output advancement programming (backplane and local output streams) . . . . . . . . . . . . . . . . . . . . . . 32 4.0 port high impedance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 lors/bors asserted low, non-32mbps mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.2 lors/bors asserted low, 32mbps mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 lors/bors asserted high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.0 bit error rate test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.0 device power-up, initialization and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.0 connection memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 local connection memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 backplane connection memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.1 memory block programming procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.0 memory built-in-self-test (bist) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.0 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1 test instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.2 test data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
zl50060/1 data sheet table of contents 5 zarlink semiconductor inc. 11.2.2.3 the device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.3 boundary scan description language (bsdl) file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.0 memory address mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.1 local data memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2 backplane data memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.3 local connection memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.4 backplane connection memory bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.0 internal register mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.0 detailed register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.2 block programming register (bpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.3 bit error rate test control register (bercr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.4 local input channel delay registers (lcdr0 to lcdr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 14.4.1 local channel delay bits 8-0 (lcd8 - lcd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 14.5 local input bit delay registers (lidr0 to lidr31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.5.1 local input delay bits 4-0 (lid[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.6 backplane input channel delay registers (bcdr0 to bcdr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.6.1 backplane channel delay bits 8-0 (bcd8 - bcd0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.7 backplane input bit delay registers (bidr0 to bidr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.7.1 backplane input delay bits 4-0 (bid[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.8 local output advancement registers (loar0 to loar31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.8.1 local output advancement bits 1-0 (loa1-loa0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.9 backplane output advancement registers (boar0 - boar31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.9.1 backplane output advancement bits 1-0 (boa1-boa0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.10 local bit error rate (ber) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.10.1 local ber start send register (lbssr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.10.2 local transmit ber length register (ltxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.10.3 local receive ber length register (lrxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.10.4 local ber start receive register (lbsrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 14.10.5 local ber count register (lbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.11 backplane bit error rate (ber) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.11.1 backplane ber start send register (bbssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.11.2 backplane transmit ber length register (btxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.11.3 backplane receive ber length register (brxblr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14.11.4 backplane ber start receive register (bbsrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14.11.5 backplane ber count register (bbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 14.12 local bit rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.12.1 local input bit rate registers (librr0 - librr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.12.2 local output bit rate registers (lobrr0 - lobrr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.13 backplane bit rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.13.1 backplane input bit rate registers (bibrr0 - bibrr31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.13.2 backplane output bit rate registers (bobrr0 - bobrr31) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.14 memory bist register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.15 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 15.0 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 16.0 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
zl50060/1 data sheet list of figures 6 zarlink semiconductor inc. figure 1 - zl50060/1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - ZL50061 pbga connections (272 pbga, 27mm x 27mm) pin diagram (as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3 - zl50060 pbga connections (256 pbga, 17mm x 17mm) pin diagram (as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4 - 16,384 x 16,384 channels (16mbps), unidirectional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5 - 8,192 x 8,192 channels (16mbps), bi-directional switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6 - 12,288 by 4,096 channels blocking bi-directional configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7 - st-bus and gci-bus input timing diagram for different data rates . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 8 - input and output frame pulse alignment for different data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9 - backplane and local input channel delay timing diagram (assuming 8mbps operation) . . . . . . . . . . 30 figure 10 - backplane and local input bit delay timing diagram for data rate of 16mbps. . . . . . . . . . . . . . . . . 31 figure 11 - backplane and local input bit delay or sampling point selection timing diagram for data rate of 8mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12 - local and backplane output advancement timing diagram for data rate of 16mbps . . . . . . . . . . . 33 figure 13 - local/backplane port external high impedance control timing (non-32mbps mode) . . . . . . . . . . . . 37 figure 14 - local and backplane port external high impedance control timing (32mbps mode) . . . . . . . . . . . . 41 figure 15 - data throughput delay with input channel delay disabled, input ch0 switched to output ch0 . . . . 43 figure 16 - data throughput delay with input channel delay disabled, input ch0 switched to output ch13 . . . 43 figure 17 - data throughput delay with input channel delay disabled, input ch13 switched to output ch0 . . . 43 figure 18 - data throughput delay with input channel delay enabled, input ch0 switched to output ch0 . . . . 44 figure 19 - data throughput delay with input channel delay enabled, input ch0 switched to output ch13 . . . 44 figure 20 - data throughput delay with input channel delay enabled, input ch13 switched to output ch0 . . . 44 figure 21 - examples of ber transmission channels on a 16mbps output stream . . . . . . . . . . . . . . . . . . . . . . 45 figure 22 - hardware reset de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23 - frame boundary conditions, st-bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 24 - frame boundary conditions, gci-bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 25 - input and output clock timing diagram for st-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 26 - input and output clock timing diagram for gci-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 27 - st-bus local/backplane data timing diagram (8mbps, 4mbps, 2mbps) . . . . . . . . . . . . . . . . . . . . . 88 figure 28 - st-bus local/backplane data timing diagram (32mbps, 16mbps). . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 29 - gci-bus local/backplane data timing diagram (8mbps, 4mbps, 2mbps) . . . . . . . . . . . . . . . . . . . . . 90 figure 30 - gci-bus local/backplane data timing diagram (32mbps, 16mbps) . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 31 - serial output and external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 32 - output driver enable (ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 33 - motorola non-multiplexed bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 34 - jtag test port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
zl50060/1 data sheet list of tables 7 zarlink semiconductor inc. table 1 - per-stream input and output data rate selection: backplane and local . . . . . . . . . . . . . . . . . . . . . . . 24 table 2 - local and backplane output enable control priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3 - l/bcsto allocation of channel control bits to output streams (non-32mbps mode) . . . . . . . . . . . . . . 35 table 4 - l/bcsto allocation of channel control bits to output streams (32mbps mode) . . . . . . . . . . . . . . . . . . 39 table 5 - variable range for input streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6 - variable range for output streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 7 - data throughput delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8 - local and backplane connection memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9 - local connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 10 - backplane connection memory in block programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 11 - address map for data and connection memory locations (a14 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 12 - local data memory (ldm) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13 - backplane data memory (bdm) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 14 - lcm bits for non-32mbps source-to-local switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 15 - lcm bits for 32mbps source-to-local switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 16 - bcm bits for non-32mbps source-to-backplane switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17 - bcm bits for 32mbps source-to-backplane switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 18 - address map for registers (a14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19 - control register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 20 - block programming register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 21 - bit error rate test control register (bercr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 22 - local input channel delay register (lcdrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 23 - local input channel delay (lcd) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 24 - local input bit delay register (lidrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 25 - local input bit delay and sampling point programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 26 - backplane input channel delay register (bcdrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 27 - backplane input channel delay (bcd) programming table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 28 - backplane input bit delay register (bidrn) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 29 - backplane input bit delay and sampling point programming table. . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 30 - local output advancement register (loar) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 31 - local output advancement (loar) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 32 - backplane output advancement register (boar) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 33 - backplane output advancement (boar) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 table 34 - local ber start send register (lbssr) bits in non-32mbps mode . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 35 - local ber start send register (lbssr) bits in 32mbps mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 36 - local ber length register (ltxblr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 37 - local receive ber length register (lrxblr) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 38 - local ber start receive register (lbsrr) bits for non-32mbps mode . . . . . . . . . . . . . . . . . . . . . . . 73 table 39 - local ber start receive register (lbsrr) bits for 32mbps mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 table 40 - local ber count register (lbcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 41 - backplane ber start send register (bbssr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 42 - backplane transmit ber length (btxblr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 43 - backplane receive ber length (brxblr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 44 - backplane ber start receive register (bbsrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 45 - backplane ber count register (bbcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 46 - local input bit rate register (librr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 47 - local input bit rate (libr) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 48 - local output bit rate register (lobrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
zl50060/1 data sheet list of tables 8 zarlink semiconductor inc. table 49 - local output bit rate (lobr) programming table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 50 - backplane input bit rate register (bibrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 52 - backplane output bit rate register (bobrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 53 - backplane output bit rate (bobrr) programming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 54 - memory bist register (mbistr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 55 - device identification register (dir) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
zl50060/1 data sheet 9 zarlink semiconductor inc. figure 2 - ZL50061 pbga connections (272 pbga, 27mm x 27mm) pin diagram (as viewed through top of package) pinout diagram: (as viewed through top of package) a1 corner identified by metallized marking 1234567891011121314151617181920 a gnd ic_gnd bsto5 bsto4 bsto2 a2 vdd_ core a8 a11 a14 ds ode dta tck bcsto1 lcsto3 lsto0 lsto1 lsto2 nc b bsto6 bsto7 bsto8 vdd_ core bsto1 nc a5 a7 a10 nc cs vdd_ core tdi trst bcsto2 lcsto2 ic_gnd lsto3 lsto4 lsto5 c bsto9 bsto10 ic_gnd bsto3 bsto0 a1 a4 a6 nc a13 r/w reset tdo bcsto0 bcsto3 lcsto1 lcsto0 lsto6 lsto7 lsto8 d bsto11 bsto12 bsto13 gnd a0 vdd_io a3 gnd a9 a12 vdd_io tms gnd vdd_ core vdd_io ic_gnd gnd lsto9 lsto10 lsto11 e bsto14 bsto15 bsto16 bsto17 lsto12 lsto13 lsto14 lsto15 f bsto18 bsto19 bsto20 vdd_io vdd_io lsto16 lsto17 lsto18 g bsto21 bsto22 bsto23 bsto24 lsto19 lsto20 lsto21 lsto22 h bsto25 bsto26 bsto27 gnd gnd lsto23 lsto24 lsto25 j bsto28 bsto29 bsto30 bsto31 gnd gnd gnd gnd lsto26 lsto27 lsto28 lsto29 k vdd_ core bors bsti0 vdd_io gnd gnd gnd gnd lsto30 lsto31 lors vdd_ core l bsti1 bsti2 bsti3 bsti4 gnd gnd gnd gnd vdd_io lsti0 lsti1 lsti2 m bsti5 bsti6 bsti7 bsti8 gnd gnd gnd gnd lsti3 lsti4 lsti5 lsti6 n bsti9 bsti10 vdd_ core gnd gnd lsti7 lsti8 lsti9 p bsti11 bsti12 bsti13 bsti14 lsti10 vdd_ core lsti11 lsti12 r bsti15 bsti16 bsti17 vdd_io vdd_io lsti13 lsti14 lsti15 t bsti18 bsti19 bsti20 bsti21 vdd_ core lsti16 lsti17 lsti18 u bsti22 nc nc gnd bsti28 vdd_io d10 gnd d4 vdd_io gnd vdd_ pll gnd fp8i vdd_io vdd_ core gnd lsti19 lsti20 lsti21 v vdd_ core nc nc bsti29 vdd_ core d13d9d7d3d0ic_gndncc8o fp8o nc nc lsti22 lsti23 lsti24 lsti25 w bsti23 bsti24 bsti25 bsti30 d15 d12 d8 d6 d2 ic_gnd ic_gnd c8i c16o fp16o nc nc nc lsti26 lsti27 nc y bsti26 bsti27 nc bsti31 d14 d11 vdd_ core d5 d1 ic_gnd vdd_ core ic_ open ic_ open vdd_ core nc nc lsti29 lsti30 lsti31 lsti28
zl50060/1 data sheet 10 zarlink semiconductor inc. figure 3 - zl50060 pbga connections (256 pbga, 17mm x 17mm) pin diagram (as viewed through top of package) pinout diagram: (as viewed through top of package) a1 corner identified by metallized marking 12345678910111213141516 a a0a1a2a3a4ds r/w cs bcsto0 bcsto1 bcsto2 bcsto3 lcsto3 lcsto2 lcsto1 lcsto0 bbsto0bsto1bsto2bsto3a5a6a7a8a9odereset tms lsto0 lsto1 lsto2 lsto3 c bsto4 bsto5 bsto6 bsto7 a10 a11 a12 a13 a14 dta tdi tdo lsto4 lsto5 lsto6 lsto7 d bsto8 bsto9 bsto10 bsto11 bors ic_gnd ic_gnd ic_gnd ic_gnd tck trst lors lsto8 lsto9 lsto10 lsto11 e bsto12 bsto13 bsto14 bsto15 vdd_io vdd_io vdd_ core vdd_ core vdd_ core vdd_ core vdd_io vdd_io lsto12 lsto13 lsto14 lsto15 f bsto16 bsto17 bsto18 bsto19 vdd_io vdd_ core gnd gnd gnd gnd vdd_ core vdd_io lsto16 lsto17 lsto18 lsto19 g bsto20 bsto21 bsto22 bsto23 vdd_io gnd gnd gnd gnd gnd gnd vdd_io lsto20 lsto21 lsto22 lsto23 h bsto24 bsto25 bsto26 bsto27 vdd_io gnd gnd gnd gnd gnd gnd vdd_io lsto24 lst25 lsto26 lsto27 j bsto28 bsto29 bsto30 bsto31 vdd_ core gnd gnd gnd gnd gnd gnd vdd_ core lsto28 lsto29 lsto30 lsto31 k bsti0 bsti1 bsti2 bsti3 vdd_ core gnd gnd gnd gnd gnd gnd vdd_ core lsti0 lsti1 lsti2 lsti3 l bsti4 bsti5 bsti6 bsti7 vdd_io vdd_ core vdd_ core gnd gnd vdd_ core vdd_ core vdd_io lsti4 lsti5 lsti6 lsti7 m bsti8 bsti9 bsti10 bsti11 vdd_io d3 d2 d1 d0 vdd_ pll nc vdd_io lsti8 lsti9 lsti10 lsti11 n bsti12 bsti13 bsti14 bsti15 bsti16 d7 d6 d5 d4 ic_ open ic_ open lsti12 lsti13 lsti14 lsti15 lsti16 p bsti17 bsti18 bsti19 bsti20 bsti21 d11 d10 d9 d8 c16o fp16o lsti17 lsti18 lsti19 lsti20 lsti21 r bsti22 bsti23 bsti24 bsti25 bsti26 d15 d14 d13 d12 fp8 o fp8i lsti22 lsti23 lsti24 lsti25 lsti26 t bsti27 bsti28 bsti29 bsti30 bsti31 ic_gnd ic_gnd ic_gnd ic_gnd c8i c8o lsti27 lsti28 lsti29 lsti30 lsti31
zl50060/1 data sheet 11 zarlink semiconductor inc. pin description pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description device timing c8i w12 t10 master clock (5v tolerant schmitt-triggered input). this pin accepts an 8.192mhz clock. the internal frame boundary is aligned with the clock falling or rising edge, as controlled by the c8ipol bit in the control register. input data on both the backplane and local sides (bsti0-31 and lsti0-31) must be aligned to this clock and the accompanying input frame pulse, fp8i . fp8i u14 r11 frame pulse input (5v tolerant schmitt-triggered input) . when the frame pulse width bit (fpw) of the control register is low (default), this pin accepts a 122ns-wide frame pulse. when the fpw bit is high, this pin accepts a 244ns-wide frame pulse. the device will automatically detect whether an st-bus or gci-bus style frame pulse is applied. input data on both the backplane and local sides (bsti0-31 and lsti0-31) must be aligned to this frame pulse and the accompanying input clock, c8i . c8o v13 t11 c8o output clock (5v tolerant three-state output). this pin outputs an 8.192mhz clock generated within the device. the clock falling edge or rising edge is aligned with the output frame boundary presented on fp8o ; this edge polarity alignment is controlled by the copol bit of the control register. output data on both the backplane and local sides (bsto0-31 and lsto0-31) will be aligned to this clock and the accompanying output frame pulse, fp8o . fp8o v14 r10 frame pulse output (5v tolerant three-state output). when the frame pulse width bit (fpw) of the control register is low (default), this pin outputs a 122ns-wide frame pulse. when the fpw bit is high, this pin outputs a 244ns-wide frame pulse. the frame pulse, running at 8khz rate, will have the same format (st-bus or gci-bus) as the input frame pulse (fp8i ). output data on both the backplane and local sides (bsto0-31 and lsto0-31) will be aligned to this frame pulse and the accompanying output clock, c8o . c16o w13 p10 c16o output clock (5v tolerant three-state output). this pin outputs a 16.384mhz clock generated within the device. the clock falling edge or rising edge is aligned with the output frame boundary presented on fp16o ; this edge polarity alignment is controlled by the copol bit of the control register. output data on both the backplane and local sides (bsto0-31 and lsto0-31) will be aligned to this clock and the accompanying output frame pulse, fp16o .
zl50060/1 data sheet 12 zarlink semiconductor inc. fp16o w14 p11 frame pulse output (5v tolerant three-state output). when the frame pulse width bit (fpw) of the control register is low (default), this pin outputs a 61ns-wide frame pulse. when the fpw bit is high, this pin outputs a 122ns-wide frame pulse. the frame pulse, running at 8khz rate, will have the same format (st-bus or gci-bus) as the input frame pulse (fp8i ). output data on both the backplane and local sides (bsto0-31 and lsto0-31) will be aligned to this frame pulse and the accompanying output clock, c16o . backplane and local inputs bsti0-15 k3, l1, l2, l3, l4, m1, m2, m3, m4, n1, n2, p1, p2, p3, p4, r1 k1, k2, k3, k4, l1, l2, l3, l4, m1, m2, m3, m4, n1, n2, n3, n4 backplane serial input streams 0 to 15 (5v tolerant inputs with internal pull-downs). in backplane non-32mbps mode, these pins accept serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each input stream. in backplane 32mbps mode, these pins accept serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). bsti16-31 r2, r3, t1, t2, t3, t4, u1, w1, w2, w3, y1, y2, u5, v4, w4, y4 n5, p1, p2, p3, p4, p5, r1, r2, r3, r4, r5, t1, t2, t3, t4, t5 backplane serial input streams 16 to 31 (5v tolerant inputs with internal pull-downs). in backplane non-32mbps mode, these pins accept serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each input stream. in backplane 32mbps mode, these pins are unused and should be externally connected to a defined logic level. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 13 zarlink semiconductor inc. lsti0-15 l18, l19, l20, m17, m18, m19, m20, n18, n19, n20, p17, p19, p20, r18, r19, r20 k13, k14, k15, k16, l13, l14, l15, l16, m13, m14, m15, m16, n12, n13, n14, n15 local serial input streams 0 to 15 (5v tolerant inputs with internal pull-downs). in local non-32mbps mode, these pins accept serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each input stream. in local 32mbps mode, these pins accept serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). lsti16-31 t18, t19, t20, u18, u19, u20, v17, v18, v19, v20, w18, w19, y20, y17, y18, y19 n16, p12, p13, p14, p15, p16, r12, r13, r14, r15, r16, t12, t13, t14, t15, t16 local serial input streams 16 to 31 (5v tolerant inputs with internal pull-downs). in local non-32mbps mode, these pins accept serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each input stream. in local 32mbps mode, these pins are unused and should be externally connected to a defined logic level. backplane and local outputs and control ode a12 b10 output drive enable (5v tolerant input with internal pull-up) . an asynchronous input providing output enable control to the bsto0-31, lsto0-31, bcsto0-3, and lcsto0-3 outputs. when low, the bsto0-31 and lsto0-31 outputs are driven high or high impedance (dependent on the bors and lors pin settings respectively) and the outputs bcsto0-3 and lcsto0-3 are driven low. when high, the outputs bsto0-31, lsto0-31, bcsto0-3, and lcsto0-3 are enabled. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 14 zarlink semiconductor inc. bors k2 d5 backplane output reset state (5v tolerant input with internal pull-down) . when this input is low, the device will initialize with the bsto0-31 outputs driven high, and the bcsto0-3 outputs driven low. following initialization, the backplane stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by outputs bcsto0-3. when this input is high, the device will initialize with the bsto0-31 outputs at high impedance and the bcsto0-3 outputs driven low. following initialization, the backplane stream outputs may be set active or high impedance using the ode pin or on a per-channel basis with the be bit in the backplane connection memory. bsto0-15 c5, b5, a5, c4, a4, a3, b1, b2, b3, c1, c2, d1, d2, d3, e1, e2 b1, b2, b3, b4, c1, c2, c3, c4, d1, d2, d3, d4, e1, e2, e3, e4 backplane serial output streams 0 to 15 (5v tolerant, three-state outputs with slew-rate control) . in backplane non-32mbps mode, these pins output serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each output stream. in backplane 32mbps mode, these pins output serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). refer to the descriptions of the bors and ode pins for control of the output high or high impedance state. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 15 zarlink semiconductor inc. bsto16-31 e3, e4, f1, f2, f3, g1, g2, g3, g4, h1, h2, h3, j1, j2, j3, j4 f1, f2, f3, f4, g1, g2, g3, g4, h1, h2, h3, h4, j1, j2, j3, j4 backplane serial output streams 16 to 31 (5v tolerant, three-state outputs with slew-rate control). in backplane non-32mbps mode, these pins output serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each output stream. these pins are unused when the backplane 32mbps mode is selected. therefore, the value output on these pins during backplane 32mbps mode (either driven-high or high impedance) is dependent on the configuration of the bors pin. refer to the descriptions of the bors and ode pins for control of the output high or high impedance state. bcsto0-3 c14, a15, b15, c15 a9, a10, a11, a12 backplane output channel high impedance control (5v tolerant, three-state outputs). these pins control external buffering individually for a set of backplane output streams on a per-channel basis. when low, the external output buffer will be tri-stated. when high, the external output buffer will be enabled. in backplane non-32mbps mode (stream rates 2mbps to 16mbps): bcsto0 is the output enable for bsto0,4,8,12,16,20,24,28 bcsto1 is the output enable for bsto1,5,9,13,17,21,25,29 bcsto2 is the output enable for bsto2,6,10,14,18,22,26,30 bcsto3 is the output enable for bsto3,7,11,15,19,23,27,31. in backplane 32mbps mode (stream rate 32mbps): bcsto0 is the output enable for bsto0,4,8,12 bcsto1 is the output enable for bsto1,5,9,13 bcsto2 is the output enable for bsto2,6,10,14 bcsto3 is the output enable for bsto3,7,11,15. refer to the descriptions of the bors and ode pins for control of the output low or active state. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 16 zarlink semiconductor inc. lors k19 d12 local output reset state (5v tolerant input with internal pull-down) . when this input is low, the device will initialize with the lsto0-31 outputs driven high, and the lcsto0-3 outputs driven low. following initialization, the local stream outputs are always active and a high impedance state, if required on a per-channel basis, may be implemented with external buffers controlled by outputs lcsto0-3. when this input is high, the device will initialize with the lsto0-31 outputs at high impedance and the lcsto0-3 outputs driven low. following initialization, the local stream outputs may be set active or high impedance using the ode pin or on a per-channel basis with the le bit in the local connection memory. lsto0-15 a17, a18, a19, b18, b19, b20, c18, c19, c20, d18, d19, d20, e17, e18, e19, e20 b13, b14, b15, b16, c13, c14, c15, c16, d13, d14, d15, d16, e13, e14, e15, e16 local serial output streams 0 to 15 (5v tolerant three-state outputs with slew-rate control) . in local non-32mbps mode, these pins output serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each output stream. in local 32mbps mode, these pins output serial tdm data streams at a fixed data rate of 32.768mbps (with 512 channels per stream). refer to the descriptions of the lors and ode pins for control of the output high or high impedance state. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 17 zarlink semiconductor inc. lsto16-31 f18, f19, f20, g17, g18, g19, g20, h18, h19, h20, j17, j18, j19, j20, k17, k18 f13, f14, f15, f16, g13, g14, g15, g16, h13, h14, h15, h16, j13, j14, j15, j16 local serial output streams 16 to 31 (5v tolerant three-state outputs with slew-rate control) . in local non-32mbps mode, these pins output serial tdm data streams at a data rate of: 16.384mbps (with 256 channels per stream), 8.192mbps (with 128 channels per stream), 4.096mbps (with 64 channels per stream) or 2.048mbps (with 32 channels per stream). the data rate is independently programmable for each output stream. these pins are unused when the local 32mbps mode is selected. therefore, the value output on these pins during local 32mbps mode (either driven-high or high impedance) is dependent on the configuration of the lors pin. refer to the descriptions of the lors and ode pins for control of the output high or high impedance state. lcsto0-3 c17, c16, b16, a16 a16, a15, a14, a13 local output channel high impedance control (5v tolerant three-state outputs). these pins control external buffering individually for a set of local output streams on a per-channel basis. when low, the external output buffer will be tri-stated. when high, the external output buffer will be enabled. in local non-32mbps mode (stream rate 2mbps to 16mbps): lcsto0 is the output enable for lsto0,4,8,12,16,20,24,28 lcsto1 is the output enable for lsto1,5,9,13,17,21,25,29 lcsto2 is the output enable for lsto2,6,10,14,18,22,26,30 lcsto3 is the output enable for lsto3,7,11,15,19,23,27,31. in local 32mbps mode (stream rate 32mbps): lcsto0 is the output enable for lsto0,4,8,12 lcsto1 is the output enable for lsto1,5,9,13 lcsto2 is the output enable for lsto2,6,10,14 lcsto3 is the output enable for lsto3,7,11,15. refer to descriptions of the lors and ode pins for control of the output low or active state. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 18 zarlink semiconductor inc. microprocessor port signals a0 - a14 d5, c6, a6, d7, c7, b7, c8, b8, a8, d9, b9, a9, d10, c10, a10 a1, a2, a3, a4, a5, b5, b6, b7, b8, b9, c5, c6, c7, c8, c9 address 0 - 14 (5v tolerant inputs). these pins form the 15-bit address bus to the internal memories and registers. a0 = lsb d0 - d15 v10, y9, w9, v9, u9, y8, w8, v8, w7, v7, u7, y6, w6, v6, y5, w5 m9, m8, m7, m6, n9, n8, n7, n6, p9, p8, p7, p6, r9, r8, r7, r6 data bus 0 - 15 (5v tolerant inputs/outputs with slew-rate control). these pins form the 16-bit data bus of the microprocessor port. d0 = lsb cs b11 a8 chip select (5v tolerant input). active low input used by the microprocessor to enable the microprocessor port access. note that a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access. ds a11 a6 data strobe (5v tolerant input). this active low input works in conjunction with cs to enable the microprocessor port read and write operations. note that a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access. r/w c11 a7 read/write (5v tolerant input). this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. dta a13 c10 data transfer acknowledgment (5v tolerant three-state output). this active low output indicates that a data bus transfer is complete. a pull-up resistor is required to hold a high level. note that a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 19 zarlink semiconductor inc. reset c12 b11 device reset (5v tolerant input with internal pull-up). this input (active low) asynchronously applies reset and synchronously releases reset to the device. in the reset state, the outputs lsto0-31 and bsto0-31 are set to a high or high impedance state, depending on the state of the lors and bors external control pins, respectively. the assertion of reset causes the lcsto0-3 and bcsto0-3 pins to be driven low (refer to table 2). the assertion of this pin also clears the device registers and internal counters. refer to section 8.3 on page 47 for the timing requirements regarding this reset signal . jtag control signals tck a14 d10 test clock (5v tolerant input). provides the clock to the jtag test logic. tms d12 b12 test mode select (5v tolerant input with internal pull-up) . jtag signal that controls the state transitions of the tap controller. tdi b13 c11 test serial data in (5v tolerant input with internal pull-up). jtag serial test instructions and data are shifted in on this pin. tdo c13 c12 test serial data out (5v tolerant three-state output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in a high impedance state when jtag is not enabled. trst b14 d11 test reset (5v tolerant input with internal pull-up). asynchronously initializes the jtag tap controller to the test-logic-reset state. this pin must be pulsed low during power-up for jtag testing. this pin must be held low for normal functional operation of the device. power and ground pins v dd_io d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, u15 e5, e6, e11, e12, f5, f12, g5, g12, h5, h12, l5, l12, m5, m12 power supply for periphery circuits: +3.3v v dd_core a7, b4, b12, d14, k1, k20, n3, p18, t17, u16, v1, v5, y7, y11, y14 e7, e8, e9, e10, f6, f11, j5, j12, k5, k12, l6, l7, l10, l11 power supply for core circuits: +1.8v pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 20 zarlink semiconductor inc. v dd_pll u12 m10 power supply for analog pll: +1.8v v ss (gnd) a1, d4, d8, d13, d17, h4, h17, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, n4, n17, u4, u8, u11, u13, u17 f7, f8, f9, f10, g6, g7, g8, g9, g10, g11, h6, h7, h8, h9, h10, h11, j6, j7, j8, j9, j10, j11, k6, k7, k8, k9, k10, k11, l8, l9 ground. unused pins nc a20, b6, b10, c9, u2, u3, v2, v3, v12, v15, v16, w15, w16, w17, w20, y3, y15, y16 m11 no connects. these pins are not used and can be tied high, low, or left unconnected. ic_open y12, y13 n10, n11 internal connections - open. these pins must be left unconnected. ic_gnd a2, b17, c3, d16, v11, w10, w11, y10 d6, d7, d8, d9, t6, t7, t8, t9 internal connections - gnd. these pins must be tied low. pin description (continued) pin name ZL50061 package coordinates (272-ball pbga) zl50060 package coordinates (256-ball pbga) description
zl50060/1 data sheet 21 zarlink semiconductor inc. 1.0 unidirectional and bi-directional switching applications the zl50060/1 has a maximum capacity of 16,384 input channels and 16,384 output channels. this is calculated from the maximum number of streams and channels: 64 input streams (32 backplane, 32 local) at 16.384mbps and 64 output streams (32 backplane, 32 local) at 16.384mbps. a typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in figure 4 below. figure 4 - 16,384 x 16,384 channels (16mbps), unidirectional switching in this system, the backplane and local input streams are combined, and the backplane and local output streams are combined, so that the switch appears as a 64 input stream by 64 output stream switch. this gives the maximum 16,384 x 16,384 channel capacity. often a system design needs to differentiate between a backplane and a local side, or it needs to put the switch in a bi-directional configuration. in this case, the zl50060/1 can be used as shown in figure 5 to give 8,192 x 8,192 channel bi-directional capacity. figure 5 - 8,192 x 8,192 channels (16mbps), bi-directional switching in this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the backplane side, as well as 8,192 input channels and 8,192 output channels on the local side. note that some or all of the output channels on one side can come from the other side, e.g., backplane input to local output switching. note that in either configuration, the backplane port can be operated in the backplane 32mbps mode, providing 512 channels on each of the 16 available input and output streams (bsti0-15 and bsto0-15) operating at a data rate of 32.768mbps, in conjunction with the local streams (lsti0-31 and lsto0-31) operating at 16.384mbps (local non-32mbps mode) or in conjunction with the local streams (lsti0-15 and lsto0-15) operating at 32.768mbps (local 32mbps mode). similarly, the local port can be operated in the local 32mbps mode, providing 512 channels on each of the 16 available input and output streams (lsti0-15 and lsto0-15) operating at a data rate of 32.768mbps, in conjunction with the backplane streams (bsti0-31 and bsto0-31) operating at 16.384mbps (backplane non-32mbps mode) or in conjunction with the backplane streams (bsti0-15 and bsto0-15) operating at 32.768mbps (backplane 32mbps mode). zl50060/1 32 streams 32 streams 32 streams 32 streams bsti0-31 lsti0-31 bsto0-31 lsto0-31 input output zl50060/1 32 streams 32 streams 32 streams 32 streams bsti0-31 bsto0-31 lsto0-31 lsti0-31 backplane local
zl50060/1 data sheet 22 zarlink semiconductor inc. the modes in which one port operates in 32mbps mode while the other port operates in non-32mbps mode allow data rate conversion between 32.768mbps and 16.384mbps without loss to the switching capacity. 1.1 flexible configuration the zl50060/1 can be configured as a 16k by 16k non-blocking unidirectional digital switch, an 8k by 8k non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities. 1.1.1 non-blocking unidirectional configuration (typical system configuration) because the input and output drivers are synchronous, the user can combine input backplane streams and input local streams as well as output backplane streams and output local streams to increase the total number of input and output streams of the switch in a unidirectional configuration, as shown in figure 4. ? 16,384-channel x 16,384-channel non-blocking switching from input to output streams 1.1.2 non-blocking bi-directional configuration another typical application is to configure the zl50060/1 as a non-blocking 8k by 8k bi-directional switch, as shown in figure 5: ? 8,192-channel x 8,192-channel non-blocking switching from backplane input to local output streams ? 8,192-channel x 8,192-channel non-blocking switching from local input to backplane output streams ? 8,192-channel x 8,192-channel non-blocking switching from backplane input to backplane output streams ? 8,192-channel x 8,192-channel non-blocking switching from local input to local output streams 1.1.3 blocking bi-directional configuration the zl50060/1 can be configured as a blocking bi-directional switch if it is an application requirement. for example, it can be configured as a 12k by 4k bi-directional blocking switch, as shown in figure 6: ? 12,288-channel x 4,096-channel blocking switching from backplane input to local output streams ? 4,096-channel x 12,288-channel blocking switching from local input to backplane output streams ? 12,288-channel x 12,288-channel non-blocking switching from backplane input to backplane output streams ? 4,096-channel x 4,096-channel non-blocking switching from local input to local output streams figure 6 - 12,288 by 4,096 channels blocking bi-directional configuration zl50060/1 12k by 12k lsto16-31 lsti16-31 4k by 4k lsti0-15 bsti0-31 bsto0-31 lsto0-15 12k by 4k 4k by 12k total 16 streams input and 16 streams output total 48 streams input and 48 streams output
zl50060/1 data sheet 23 zarlink semiconductor inc. 2.0 functional description 2.1 switching configuration the device supports five switching configurations: (1) unidirectional switch, (2) backplane-to-local, (3) local-to-backplane, (4) backplane-to-backplane, and (5) local-to-local. the following sections describe the switching paths in detail. configurations (2) - (5) enable a non-blocking bi-directional switch with 8,192 backplane input/output channels at backplane stream data rates of 16.384mbps or 32.768mbps, and 8,192 local input/output channels at local stream data rates of 16.384mbps or 32.768mbps. the switching paths of configurations (2) to (5) may be operated simultaneously. when the lower data-rates of 8.192, 4.096 and 2.048mbps are included, there will be a corresponding reduction in switch capacity although conversion between differing rates will be maintained. 2.1.1 unidirectional switch the device can be configured as a 16,384 x 16,384 unidirectional switch by grouping together all input streams and all output streams. all streams can be operated at a data rate of 16.384mbps or 32.768mbps, or a combination of 16.384mbps and 32.768mbps (i.e., one rate on the local streams and the other rate on the backplane streams). lower data rates may be used with a corresponding reduction in switch capacity. 2.1.2 backplane-to-local path the device can provide data switching between the backplane input port and the local output port. the local connection memory determines the switching configurations. 2.1.3 local-to-backplane path the device can provide data switching between the local input port and the backplane output port. the backplane connection memory determines the switching configurations. 2.1.4 backplane-to-backplane path the device can provide data switching between the backplane input and output ports. the backplane connection memory determines the switching configurations. 2.1.5 local-to-local path the device can provide data switching between the local input and output ports. the local connection memory determines the switching configurations. 2.1.6 port data rate modes and selection the bit rate for each input stream is selected by writing to dedicated input bit rate registers, bibrr0 to bibrr31 for backplane input bit rate registers (see table 50) and librr0 to librr31 for local input bit rate registers (see table 46). the bit rate for each output stream is selected by writing to dedicated output bit rate registers, bobrr0 to bobrr31 for backplane output bit rate registers (see table 52) and lobrr0 to lobrr31 for local output bit rate registers (see table 48). if the backplane 32mbps mode is selected by setting the control register bit mode32b high, the settings in bibrrn and bobrrn are ignored. similarly, if the local 32mbps mode is selected by setting the control register bit mode32l high, the settings in librrn and lobrrn are ignored.
zl50060/1 data sheet 24 zarlink semiconductor inc. table 1 - per-stream input and output data rate selection: backplane and local 2.1.7 local port rate selection the local port has 32 input (lsti0-31) and 32 output (lsto0-31) data streams. the local streams can be operated in one of two modes, local non-32mbps mode and local 32mbps mode. the local stream data rates are not affected by the operating mode of the backplane port. the operating mode of the local side is determined by the state of the control register bit mode32l. setting this bit high will invoke the local 32mbps mode. setting the bit low will invoke the non-32mbps mode. the default value of this bit on device reset is low. the timing of the input and output clocks and frame pulses is shown in figure 8, ?input and output frame pulse alignment for different data rates? on page 28. local non-32mbps mode: each of the local streams (lsti0-31 and lsto0-31) can be independently programmed for a data rate of 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps. local 32mbps mode: 16 of the local input streams (lsti0-15) and 16 of the local output streams (lsto0-15) operate at a fixed rate of 32.768mbps. in this mode, the remaining input and output streams are unused. 2.1.7.1 local input port the input traffic on the local streams are aligned based on the fp8i and c8i input timing signals. each input stream, lsti0-31, can be individually set to operate at 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps by programming the libr1-0 bits in the local input bit rate register (librr0-31). the local streams can also be set to operate at 32.768mbps. when the mode32l bit in the control register is set high, the first 16 input streams, lsti0-15, operate at 32.768mbps and the remaining 16 streams, lsti16-31, will not be used and must be connected to a defined logic level. stream numbers rate selection capability (for each individual stream) local input streams - lsti0-15 2.048, 4.096, 8.192 or 16.384mbps in local non-32mbps mode. all streams at 32.768mbps in local 32mbps mode. local input streams - lsti16-31 2.048, 4.096, 8.192 or 16.384mbps in local non-32mbps mode. unused in local 32mbps mode. backplane input streams - bsti0-15 2.048, 4.096, 8.192 or 16.384mbps in backplane non-32mbps mode. all streams at 32.768mbps in backplane 32mbps mode. backplane input streams - bsti16-31 2.048, 4.096, 8.192 or 16.384mbps in backplane non-32mbps mode. unused in backplane 32mbps mode. local output streams - lsto0-15 2.048, 4.096, 8.192 or 16.384mbps in local non-32mbps mode. all streams at 32.768mbps in local 32mbps mode. local output streams - lsto16-31 2.048, 4.096, 8.192 or 16.384mbps in local non-32mbps mode. unused in local 32mbps mode. backplane output streams - bsto0-15 2.048, 4.096, 8.192 or 16.384mbps in backplane non-32mbps mode. all streams at 32.768mbps in backplane 32mbps mode. backplane output streams - bsto16-31 2.048, 4.096, 8.192 or 16.384mbps in backplane non-32mbps mode. unused in backplane 32mbps mode.
zl50060/1 data sheet 25 zarlink semiconductor inc. 2.1.7.2 local output port the output traffic on the local streams are aligned based on the fp8o and c8o output timing signals. operation of stream data in connection mode or message mode is determined by the state of the lmm bit of the local connection memory. the channel high impedance state is controlled by the le bit of the local connection memory. the data source (i.e. from the local or backplane data memory) is determined by the lsrc bit of the local connection memory. refer to section 9.1, local connection memory, and section 12.3, local connection memory bit definition for more details. each output stream, lsto0-31, can be individually set to operate at 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps by programming the lobr1-0 bits in the local output bit rate register (lobrr0-31). the local streams can also be set to operate at 32.768mbps. when the mode32l bit in the control register is set high, the first 16 output streams, lsto0-15, operate at 32.768mbps and the remaining 16 streams, lsto16-31, will not be used and must be connected to a defined logic level. 2.1.8 backplane port rate selection the backplane port has 32 input (bsti0-31) and 32 output (bsto0-31) data streams. the backplane streams can be operated in one of two modes, backplane non-32mbps mode and backplane 32mbps mode. the backplane stream data rates are not affected by the operating mode of the local port. the operating mode of the backplane side is determined by the state of the control register bit mode32b. setting this bit high will invoke the backplane 32mbps mode. setting the bit low will invoke the non-32mbps mode. the default value of this bit on device reset is low. the timing of the input and output clocks and frame pulses is shown in figure 8, ?input and output frame pulse alignment for different data rates? on page 28. backplane non-32mbps mode: each of the backplane streams (bsti0-31 and bsto0-31) can be independently programmed for a data rate of 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps. backplane 32mbps mode: 16 of the backplane input streams (bsti0-15) and 16 of the backplane output streams (bsto0-15) operate at a fixed rate of 32.768mbps. in this mode, the remaining input and output streams are unused. 2.1.8.1 backplane input port the input traffic on the backplane streams are aligned based on the fp8i and c8i input timing signals. each input stream, bsti0-31, can be individually set to operate at 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps by programming the bibr1-0 bits in the backplane input bit rate register (bibrr0-31). the backplane streams can also be set to operate at 32.768mbps. when the mode32b bit in the control register is set high, the first 16 input streams, bsti0-15, operate at 32.768mbps and the remaining 16 streams, bsti16-31, will not be used and must be connected to a defined logic level. 2.1.8.2 backplane output port the output traffic on the backplane streams are aligned based on the fp8o and c8o output timing signals. operation of stream data in connection mode or message mode is determined by the state of the bmm bit of the backplane connection memory and the channel high impedance state is controlled by the be bit of the backplane connection memory. the data source (i.e. from the local or backplane data memory) is determined by the bsrc bit of the backplane connection memory. refer to section 9.2, backplane connection memory and section 12.4, backplane connection memory bit definition for more details. each output stream, bsto0-31, can be individually set to operate at 2.048mbps, 4.096mbps, 8.192mbps or 16.384mbps by programming the bobr1-0 bits in the backplane output bit rate register (bobrr0-31). the backplane streams can also be set to operate at 32.768mbps. when the mode32b bit in the control register is set high, the first 16 output streams, bsto0-15, operate at 32.768mbps and the remaining 16 streams, bsto16-31, will not be used and must be connected to a defined logic level.
zl50060/1 data sheet 26 zarlink semiconductor inc. 2.2 frame pulse input and master input clock timing the input frame pulse (fp8i ) is an 8khz input signal active for 122ns or 244ns at the frame boundary. the fpw bit in the control register must be set according to the applied pulse width. see pin description and table 19, ?control register bits? on page 56, for details. the active state and timing of fp8i can conform either to the st-bus or to the gci-bus as shown in figure 7, st-bus and gci-bus input timing diagram for different data rates. the zl50060/1 device will automatically detect whether an st-bus or a gci-bus style frame pulse is being used for the master frame pulse (fp8i ). the output frame pulses (fp8o and fp16o ) are always of the same style (st-bus or gci-bus) as the input frame pulse. the active edge of the input clock (c8i) shall be selected by the state of the control register bit c8ipol. note that the active edge of st-bus is falling edge, which is the default mode of the device, while gci-bus uses rising edge as the active edge. although gci frame pulse will be automatically detected, to fully conform to gci-bus operation, the device should be set to use c8i rising edge as the active edge (by setting bit c8ipol high) when gci-bus is used. for the purposes of describing the device operation, the remaining part of this document assumes the st-bus frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise. in addition, the device provides fp8o , fp16o , c8o and c16o outputs to support external devices which connect to the output ports. the generated frame pulses (fp8o , fp16o ) will be provided in the same format as the master frame pulse (fp8i ). the polarity of c8o and c16o , at the frame boundary, can be controlled by the control register bit, copol. an analog phase lock loop (apll) is used to multiply the input clock frequency on c8i to generate an internal clock signal operating at 131.072mhz.
zl50060/1 data sheet 27 zarlink semiconductor inc. figure 7 - st-bus and gci-bus input timing diagram for different data rates fp8i (st-bus) (8.192mhz) 7 2 3 4 5 610 0 bsti/lsti0-31 (16mbps) st-bus 1 2 3 4 5 610 7 channel 255 channel 0 c8i (gci-bus) 0 bsti/lsti0-31 (8mbps) gci-bus channel 0 3 7 6 channel 127 5 4 (8khz) (8khz) fp8i (gci-bus) 7 bsti/lsti0-31 (4mbps) st-bus channel 0 6 0 1 channel 63 7 12 7 7 2 3 4 5 6 10 bsti/lsti0-15 (32mbps) st-bus channel 0 72 3 4 5 610 channel 1 2 310 7 2 3 4 5 6 10 channel 511 2 3 4 5 610 channel 510 76 0 0 (8.192mhz) c8i (st-bus) 0 bsti/lsti0-31 (2mbps) gci-bus channel 0 7 channel 31 0 7 0 5 4 3 2 1 67 bsti/lsti0-15 (32mbps) gci-bus channel 0 05 4 3 2 167 channel 1 5 467 05 4 3 2 167 channel 511 5 4 3 2 167 channel 510 01 0 5 4 3 2 167 7 bsti/lsti0-31 (16mbps) gci-bus 6 5 4 3 2 167 0 channel 255 channel 0 7 bsti/lsti0-31 (8mbps) st-bus channel 0 4 0 1 channel 127 2 3 65 0 7 0 bsti/lsti0-31 (4mbps) gci-bus channel 0 1 7 6 channel 63 0 7 7 bsti/lsti0-31 (2mbps) st-bus channel 0 0 channel 31 7 0
zl50060/1 data sheet 28 zarlink semiconductor inc. 2.3 input frame pulse and generated frame pulse alignment the zl50060/1 accepts a frame pulse (fp8i ) and generates two frame pulse outputs, fp8o and fp16o , which are aligned to the master frame pulse. there is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during frame n is output during frame n+2. for further details of frame pulse conditions and options, see section 14.1, control register (cr), figure 23, frame boundary conditions, st-bus operation, and figure 24, frame boundary conditions, gci-bus operation. figure 8 - input and output frame pulse alignment for different data rates the t fbos is the offset between the input frame pulse, fp8i , and the generated output frame pulse, fp8o . refer to the ?ac electrical characteristics,? on page 83. note that although the figure above shows the traditional setups of the frame pulses and clocks for both st-bus and gci-bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the fpw bit in the control register is set) as well as to use the opposite clock edge for frame-boundary determination (using the c8ipol and copol bits in the control register). see the timing diagrams in ?ac electrical characteristics,? on page 83 for all of the available configurations. 2.4 jitter tolerance improvement circuit - frame boundary discriminator to improve the jitter tolerance of the zl50060/1, a frame boundary discriminator (fbd) circuit was added to the device. this circuit is enabled by setting the control register bit fbden to high. by default the fbd is disabled. the fbd can operate in two modes, as controlled by the fbd_mode[2:0] bits of the control register. when bits fbd_mode[2:0] are set to 000 b , the fbd is set to handle lower frequency jitter only (<8khz). when bits fbd_mode[2:0] are set to 111 b , the fbd can handle both low frequency and high frequency jitter. all other values are reserved. these bits are ignored when bit fbden is low. it is strongly recommended that if bit fbden is set high, bits fbd_mode[2:0] should be set to 111 b to improve the high frequency jitter handling capability. to achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be optimized. in most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by programming all the lidr and bidr registers). this will give more allowance for sampling point variations caused ch3 ch7 ch0 ch1 ch2 bsti/lsti 0-31 (16mbps) c8o fp8o bsto/lsto 0-31 (2mbps) bsto/lsto 0-31 (4mbps) bsto/lsto0- 31 (8mbps) bsto/lsto0- 31 (16mbps) ch2 ch1 ch0 ch6 ch5 ch4 ch3 ch2 ch0 ch4 ch5 ch10 ch9 ch8 ch11 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 ch 19 ch 18 ch 17 ch 16 ch 23 ch 22 ch 21 ch 20 ch1 ch 3 ch 2 ch 1 ch 0 ch 7 ch 6 ch 5 ch 4 ch 11 ch 10 ch 9 ch 8 ch 15 ch 14 ch ch 12 13 ch 17 ch 16 ch 21 ch 20 ch ch 18 19 ch 23 ch 22 fp8i c8i ch3 ch7 ch0 ch1 ch2 (2mbps) bsti/lsti 0-31 (4mbps) bsti/lsti 0-31 ch2 ch1 ch0 ch6 ch5 ch4 ch3 ch2 ch0 ch4 ch5 ch10 ch9 ch8 ch11 ch1 bsti/lsti 0-31 (8mbps) t fbos bsto/lsto0- 15 (32mbps) ch 0 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 1617 181920 212223 24252627 28 29 3031 3233 3435 3637 3839 4041 42 4344 4546 47 bsti/lsti 0-15 (32mbps) ch 0 1 2 3 4 5 6 7 8 9 10 1112131415161718 1920 212223 24252627282930313233 3435363738394041 424344454647
zl50060/1 data sheet 29 zarlink semiconductor inc. by jitter. there are, however, some cases where data experience more delay than the timing signals. a common example is when multiple data lines are tied together to form bidirectional buses. the large bus loading may cause data to be delayed. if this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. the optimum sampling point is dependent on the application. the user should optimize the sampling point to achieve the best jitter tolerance performance. 2.5 input clock jitter tolerance input clock jitter tolerance depends on the data rate. in general, the higher the data rate, the smaller the jitter tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller. jitter tolerance can not be accurately represented by just one number. jitter of the same amplitude but different frequency spectrum can have different effect on the operation of a device. for example, a device that can tolerate 20ns of jitter of 10khz frequency may only be able to tolerate 10ns of jitter of 1mhz frequency. therefore, jitter tolerance should be represented as a spectrum over frequency. the highest possible jitter frequency is half of the carrier frequency. in the case of the zl50060/1, the input clock is 8.192mhz, and the jitter associated with this clock can have the highest frequency component at 4.096mhz. for the above reasons, jitter tolerance of the zl50060/1 has been characterized at two data rates, 16.384mbps and 32.768mbps. the lower data rates (2.048mbps, 4.096mbps, 8.192mbps) will have the same or better tolerance than that of the 16.384mbps operation. tolerance of jitter of different frequencies are shown in the ?ac electrical characteristics? section, table ?input clock jitter tolerance? on page 93. the jitter tolerance improvement circuit was enabled (control register, bit fbden set high, and bits fbd_mode[2:0] set to 111 b ), and the sampling point was optimized. 2.6 backward compatibility with mt90869 the ZL50061 is pin-to-pin compatible with zarlink?s mt90869 device. to ensure software compatibility between the two devices, the user must consider the following items: 1. the ZL50061 has enhanced input clock jitter tolerance. to maximize the jitter tolerance, the frame boundary discriminator (fbd) circuit has to be enabled by setting bits fbden and fbd_mode[2:0] in the control regis- ter high. in mt90869, these bits are un-used. the input data sampling point also needs to be optimized by pro- gramming all the lidr and bidr registers. these are described in details in section 2.4. 2. when bit error rate (ber) transmission is enabled, all the channels on all same side (local/backplane) as the target ber transmission channel(s) will be unable to switch traffic. also, the ber counters (lbcr and bbcr) will not rollover. they will saturate when they reach their maximum value. these are described in more details in section 6.0. 3. the hardware reset signal (reset ) must be de-asserted less than 12 s after the frame boundary or more than 13 s after the frame boundary, as described in section 8.3. this can be achieved, for example, by synchroniz- ing the de-assertion of the reset signal with the input frame pulse. 3.0 input and output offset programming various registers are used to control the input sampling point (delay) and the output advancement for the local and backplane streams. the following sections explain the details of these offset programming features. 3.1 input offsets control of the input channel delay and the input bit delay allows each input stream to have a different frame boundary with respect to the master frame pulse, fp8i . the use of input channel delay in combination with input bit delay enables the ch0 position to be placed anywhere within a frame to a resolution of 1/4 of the bit period.
zl50060/1 data sheet 30 zarlink semiconductor inc. 3.1.1 input channel delay programming (backplane and local input streams) by programming the backplane or local input channel delay registers (bcdr0 - bcdr31 and lcdr0 - lcdr31), users can individually assign the ch0 position of each input stream to be located at any of the channel boundaries in a frame. for delays within channel boundaries, the input bit delay programming can be used. by default, all input streams have a channel delay of zero such that ch0 is the first channel that appears after the frame boundary. figure 9 - backplane and local input channel delay timing diagram (assuming 8mbps operation) 3.1.2 input bit delay programming (backplane and local input streams) in addition to the input channel delay programming, input bit delay registers lidr0-31 and bidr0-31 work in conjunction with the smpl_mode bit in the control register to allow users to control input bit fractional delay as well as input bit sample point selection for greater flexibility when designing switch matrices for high speed operation. when smpl_mode = low (input bit fractional delay mode), bits lid[4:0] and bid[4:0] in the lidr0-31 and bidr0-31 registers respectively define the input bit fractional delay of the corresponding local and backplane stream. the total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. when smpl_mode = high (sampling point select mode), bits lid[1:0] and bid[1:0] define the input bit sampling point of the stream. the sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance for input jitter. bits lid[4:2] and bid[4:2] define the integer input bit delay, with a maximum value of 7 bits at a resolution of 1 bit. refer to figure 10 and figure 11 for input bit delay timing at 16mbps and 8mbps data rates, respectively. refer to figure 11 for input sampling point selection timing at 8mbps data rates. fp8i c8i 72 3 4 5 610 bsti/lsti0-31 channel delay = 0 ch 0 72 3 4 5 610 ch 1 2 310 72 3 4 5 610 ch127 2 3 4 5 610 ch126 76 72 3 4 5 610 bsti/lsti0-31 channel delay = 1 ch127 72 3 4 5 610 ch 0 2 310 72 3 4 5 610 ch126 2 3 4 5 610 ch125 76 72 3 4 5 610 bsti/lsti0-31 channel delay = 2 ch126 72 3 4 5 610 ch127 2 310 72 3 4 5 610 ch125 2 3 4 5 610 ch0 76 (default) channel delay,1 channel delay, 2 7
zl50060/1 data sheet 31 zarlink semiconductor inc. figure 10 - backplane and local input bit delay timing diagram for data rate of 16mbps c8i 72 3 4 5 610 bsti/lsti0-31 bit delay = 0 ch0 74 5 6 ch1 2 310 bsti/lsti0-31 bit delay = 1/4 72 3 4 5 610 bsti/lsti0-31 bit delay = 1 ch0 75 6 ch1 2 310 (default) 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 ch255 ch255 bit delay, 1/4 bit delay, 1 bsti/lsti0-31 bit delay = 1/2 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 bit delay, 1/2 bsti/lsti0-31 bit delay = 3/4 72 3 4 5 610 ch0 74 5 6 ch1 2 310 ch255 bit delay, 3/4 bsti/lsti0-31 bit delay = 7 1/2 72 3 4 5 610 ch255 74 5 6 ch0 210 ch254 bit delay, 7 1/2 bsti/lsti0-31 bit delay = 7 3/4 72 3 4 5 610 ch255 74 5 6 ch0 210 ch254 bit delay, 7 3/4 fp8i smpl_mode = low please refer to control register (section 14.1) for smpl_mode definition.
zl50060/1 data sheet 32 zarlink semiconductor inc. figure 11 - backplane and local input bit delay or sampling point selection timing diagram for data rate of 8mbps 3.2 output advancement programming (backplane and local output streams) this feature is used to advance the output channel alignment of individual local or backplane output streams with respect to the frame boundary fp8o . each output stream has its own advancement value that can be programmed by the output advancement registers. the output advancement selection is useful in compensating for various parasitic loading on the serial data output pins. the local and backplane output advancement registers, loar0 - loar31 and boar0 - boar31, are used to control the local and backplane output advancement respectively. the advancement is determined with reference to the internal system clock rate (131.072mhz). for 2mbps, 4mbps, 8mbps or 16mbps streams, the advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which converts to approximately 0ns, -15ns, -31ns or -46ns as shown in figure 12. for 32mbps streams, the advancement can be 0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7.6ns, -15ns or -23ns. c8i 7 2 3 4 5 6 bsti/lsti0-31 bid[4:0]/lid[4:0] = 00011 b ch0 1 0 ch127 sample at 3/4 point fp8i 7 2 3 4 5 6 bsti/lsti0-31 bid[4:0]/lid[4:0] = 00000 b ch0 1 0 bit delay = 0 bit (default) ch127 sample at 3/4 point smpl_mode = low c8i 7 2 3 4 5 6 bsti/lsti0-31 bid[4:0]/lid[4:0] = 00011 b ch0 1 0 ch127 sample at 2/4 point fp8i 7 2 3 4 5 6 bsti/lsti0-31 bid[4:0]/lid[4:0] = 00000 b ch0 1 0 3/4 sampling (default) ch127 sample at 3/4 point smpl_mode = high please refer to control register (section 14.1) for smpl_mode definition. bit delay = 3/4 bit 2/4 sampling
zl50060/1 data sheet 33 zarlink semiconductor inc. figure 12 - local and backplane output advancement timing diagram for data rate of 16mbps 4.0 port high impedance control the input pins, lors and bors , select whether the local ( lsto0-31 ) and backplane ( bsto0-31 ) output streams, respectively, are set to high impedance at the output of the device itself, or are always driven (active high or active low). in the latter case (i.e. always driven), a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the lcsto0-3/bcsto0-3 signals. setting lors/bors to a low state will configure the output streams, lsto0-31/bsto0-31, to transmit bi-state channel data with per-channel high impedance determined by external circuits under the control of the lcsto0-3/bcsto0-3 outputs. setting lors/bors to a high state will configure the output streams, lsto0-31/bsto0-31, of the device to invoke a high impedance output on a per-channel basis when required as controlled by the le/be bit. the state of the lors/bors pin is detected and the device configured accordingly during a reset operation, e.g. following power-up. the lors/bors pin is an asynchronous input and is expected to be hard-wired for a particular system application, although it may be driven under logic control if preferred. the local/backplane output enable control in order of highest priority is: reset , ode, osb, le/be. reset (input pin) ode (input pin) osb (control register bit) le/be (local / backplane connection memory bit) lors/bors (input pin) lsto0-31/ bsto0-31 lcsto0-3/ bcsto0-3 0xxx0highlow 0xxx1hi-zlow 10xx0highlow 10xx1hi-zlow 110x0highlow 110x1hi-zlow 11100highlow table 2 - local and backplane output enable control priority bit advancement, -2 bit advancement, -4 bit advancement, -6 fp8o system clock bsto/lsto0-31 bit advancement = 0 bsto/lsto0-31 bit advancement = -2 (default) bit advancement = -6 bsto/lsto0-31 bit advancement = -4 bsto/lsto0-31 131.072 mhz ch255 ch255 ch255 ch255 ch0 ch0 ch0 ch0 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 4 bit advancement, 0
zl50060/1 data sheet 34 zarlink semiconductor inc. 4.1 lors/bors asserted low, non-32mbps mode the data (channel control bit) transmitted by l / bcsto0-3 replicates the local/backplane output enable ( le/be ) bit of the local/backplane connection memory, with a low state indicating the channel to be set to high impedance. refer to ?local connection memory bit definition,? on page 52 and ?backplane connection memory bit definition,? on page 53 for more details. the l/bcsto0-3 pins transmit serial data (channel control bits) at 16.384mbps, with each bit representing the per-channel high impedance state for a specific stream. eight output streams are allocated to each control line as follows: ? l/bcsto0 outputs the channel control bits for streams l/bsto0, 4, 8, 12, 16, 20, 24, and 28 ? l/bcsto1 outputs the channel control bits for streams l/bsto1, 5, 9, 13, 17, 21, 25, and 29 ? l/bcsto2 outputs the channel control bits for streams l/bsto2, 6, 10, 14, 18, 22, 26 and 30 ? l/bcsto3 outputs the channel control bits for streams l/bsto3, 7, 11, 15, 19, 23, 27 and 31 the channel control bit location, within a frame period, for each channel of the local/backplane output streams is presented in table 3, l/bcsto allocation of channel control bits to output streams (non-32mbps mode). as an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to table 3: 1. the channel control bit corresponding to stream 0, channel 0, l/bsto0_ch0, is transmitted on l/bcsto0 and is advanced, relative to the frame boundary, by 10 periods of c16o . 2. the channel control bit corresponding to stream 28, channel 0, l/bsto28_ch0, is transmitted on l/bcsto0 in advance of the frame boundary by three periods of output clock, c16o . similarly, the channel control bits for l/bsto29_ch0 , l/bsto30_ch0 and l/bsto31_ch0 are advanced relative to the frame boundary by three periods of c16o , on l/bcsto1 , l/bcsto2 and l/bcsto3 , respectively. the l/bcsto0-3 pins output data at a constant data rate of 16.384mbps, independent of the data rate selected for the individual output streams, l/bsto0-31 . streams at data rates lower than 16.384mbps will have the value of their respective channel control bit repeated for the duration of the channel. the bit will be repeated twice for 8.192mbps streams, four times for 4.096mbps streams and eight times for 2.048mbps streams. the channel control bit is not repeated for 16.384mbps streams. examples are presented, with reference to table 3: 3. with stream l/bsto4 selected to operate at a data rate of 2.048mbps, the value of the channel control bit for channel 0 will be transmitted during the c16o clock period numbers 2040, 2048, 8, 16, 24, 32, 40 and 48. 4. with stream l/bsto8 operated at a data rate of 8.192mbps, the value of the channel control bit for channel 1 will be transmitted during the c16o clock period numbers 9 and 17. 11101hi-zlow 1111xactive (high or low) active (high or low) reset (input pin) ode (input pin) osb (control register bit) le/be (local / backplane connection memory bit) lors/bors (input pin) lsto0-31/ bsto0-31 lcsto0-3/ bcsto0-3 table 2 - local and backplane output enable control priority (continued)
zl50060/1 data sheet 35 zarlink semiconductor inc. allocated stream no. channel no. 2 c16o period 1 l/bcsto0 l/bcsto1 l/bcsto2 l/bcsto3 16mbps 8mbps 4mbps 2mbps 2039 0 3-1 1 2 3 ch 0 ch 0 ch 0 ch 0 2040 4 3-3 5 6 7 ch 0 ch 0 ch 0 ch 0 2041 8 9 10 11 ch 0 ch 0 ch 0 ch 0 2042 12 13 14 15 ch 0 ch 0 ch 0 ch 0 2043 16 17 18 19 ch 0 ch 0 ch 0 ch 0 2044 20 21 22 23 ch 0 ch 0 ch 0 ch 0 2045 24 25 26 27 ch 0 ch 0 ch 0 ch 0 2046 28 3-2 29 3-2 30 3-2 31 3-2 ch 0 ch 0 ch 0 ch 0 20470123ch 1ch 0ch 0ch 0 2048 4 3-3 5 6 7 ch 1 ch 0 ch 0 ch 0 frame 1 8 9 10 11 ch 1 ch 0 ch 0 ch 0 boundary 2 12 13 14 15 ch 1 ch 0 ch 0 ch 0 3 16 17 18 19 ch 1 ch 0 ch 0 ch 0 4 20 21 22 23 ch 1 ch 0 ch 0 ch 0 5 24 25 26 27 ch 1 ch 0 ch 0 ch 0 6 28 29 30 31 ch 1 ch 0 ch 0 ch 0 70123ch 2ch 1ch 0ch 0 84 3-3 5 6 7 ch 2 ch 1 ch 0 ch 0 98 3-4 9 10 11 ch 2 ch 1 ch 0 ch 0 10 12 13 14 15 ch 2 ch 1 ch 0 ch 0 11 16 17 18 19 ch 2 ch 1 ch 0 ch 0 12 20 21 22 23 ch 2 ch 1 ch 0 ch 0 13 24 25 26 27 ch 2 ch 1 ch 0 ch 0 14 28 29 30 31 ch 2 ch 1 ch 0 ch 0 150123ch 3ch 1ch 0ch 0 16 4 3-3 5 6 7 ch 3 ch 1 ch 0 ch 0 17 8 3-4 9 10 11 ch 3 ch 1 ch 0 ch 0 etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. 2029 etc. etc. etc. etc. ch 254 ch 127 ch 63 ch 31 2030 28 29 30 31 ch 254 ch 127 ch 63 ch 31 20310123ch 255ch 127ch 63ch 31 20324567ch 255ch 127ch 63ch 31 2033 8 9 10 11 ch 255 ch 127 ch 63 ch 31 2034 12 13 14 15 ch 255 ch 127 ch 63 ch 31 table 3 - l/bcsto allocation of channel control bits to output streams (non-32mbps mode)
zl50060/1 data sheet 36 zarlink semiconductor inc. note 1: clock period count is referenced to frame boundary. note 2: the channel numbers presented relate to the data rate selected for a specific stream. note 3: 3-1 to 3-4: see above for examples of channel control bits for streams of different data rates. 2035 16 17 18 19 ch 255 ch 127 ch 63 ch 31 2036 20 21 22 23 ch 255 ch 127 ch 63 ch 31 2037 24 25 26 27 ch 255 ch 127 ch 63 ch 31 2038 28 29 30 31 ch 255 ch 127 ch 63 ch 31 2039 0 3-1 1 2 3 ch 0 ch 0 ch 0 ch 0 2040 4 3-3 5 6 7 ch 0 ch 0 ch 0 ch 0 2041 8 9 10 11 ch 0 ch 0 ch 0 ch 0 2042 12 13 14 15 ch 0 ch 0 ch 0 ch 0 2043 16 17 18 19 ch 0 ch 0 ch 0 ch 0 2044 20 21 22 23 ch 0 ch 0 ch 0 ch 0 2045 24 25 26 27 ch 0 ch 0 ch 0 ch 0 2046 28 3-2 29 3-2 30 3-2 31 3-2 ch 0 ch 0 ch 0 ch 0 20470123ch 1ch 0ch 0ch 0 2048 4 3-3 5 6 7 ch 1 ch 0 ch 0 ch 0 frame 1 8 9 10 11 ch 1 ch 0 ch 0 ch 0 boundary 2 12 13 14 15 ch 1 ch 0 ch 0 ch 0 3 16 17 18 19 ch 1 ch 0 ch 0 ch 0 etc. etc. etc. etc. etc. etc. etc. etc. etc. allocated stream no. channel no. 2 c16o period 1 l/bcsto0 l/bcsto1 l/bcsto2 l/bcsto3 16mbps 8mbps 4mbps 2mbps table 3 - l/bcsto allocation of channel control bits to output streams (non-32mbps mode) (continued)
zl50060/1 data sheet 37 zarlink semiconductor inc. figure 13, local/backplane port external high impedance control timing (non-32mbps mode) shows the channel control bits for l/bcsto0 , l/bcsto1 , l/bcsto2 and l/bcsto3 in one possible scenario which includes stream l/bsto0 at a data rate of 16.384mbps, l/bsto1 at 8.192mbps, l/bsto6 at 4.096mbps and l/bsto7 at 2.048mbps. all remaining streams are operated at a data rate of 16.384mbps. figure 13 - local/backplane port external high impedance control timing (non-32mbps mode) chan 0 bit 7 chan 0 bit 6 chan 63 bit 1 chan 63 bit 0 chan 0 bit 7 chan 63 bit 0 7 6 5 4 3 2 3 2 1 0 5 4 1 6 0 7 7 6 0 chan 0 bit 7 chan 0 bit 6 chan 0 bit 5 chan 0 bit 4 chan 127 bit 3 chan 127 bit 2 chan 127 bit 1 chan 127 bit 0 chan 0 bit 7 chan 127 bit 0 channel 0 bit 7 channel 31 bit 0 chan 0 bit 7 chan 31 bit 0 l/bcsto0 l/bsto0 (16mbps) l/bsto1 (8mbps) l/bsto6 (4mbps) l/bsto7 (2mbps) c8o fp8o ch 1 l/bsto0 ch 1 l/bsto4 ch 1 l/bsto8 ch 1 l/bsto12 ch 1 l/bsto16 ch 1 l/bsto20 ch 1 l/bsto24 ch 1 l/bsto28 ch 2 l/bsto0 ch 2 l/bst04 ch 0 l/bsto8 ch 0 l/bsto12 ch 0 l/bsto16 ch 0 l/bsto20 ch 0 l/bsto24 ch 0 l/bsto28 ch 1 l/bsto0 ch 1 l/bsto4 ch 1 l/bsto8 ch 1 l/bsto12 ch 0 l/bsto1 ch 1 l/bsto5 ch 1 l/bsto9 ch 1 l/bsto13 ch 1 l/bsto17 ch 1 l/bsto21 ch 1 l/bsto25 ch 1 l/bsto29 ch 1 l/bsto1 ch 2 l/bsto5 ch 0 l/bsto9 ch 0 l/bsto13 ch 0 l/bsto17 ch 0 l/bsto21 ch 0 l/bsto25 ch 0 l/bsto29 ch 0 l/bsto1 ch 1 l/bsto5 ch 1 l/bsto9 ch 1 l/bsto13 ch 1 l/bsto2 ch 0 l/bsto6 ch 1 l/bsto10 ch 1 l/bsto14 ch 1 l/bsto18 ch 1 l/bsto22 ch 1 l/bsto26 ch 1 l/bsto30 ch 2 l/bsto2 ch 0 l/bsto6 ch 0 l/bsto10 ch 0 l/bsto14 ch 0 l/bsto18 ch 0 l/bsto22 ch 0 l/bsto26 ch 0 l/bsto30 ch 1 l/bsto2 ch 0 l/bsto6 ch 1 l/bsto10 ch 1 l/bsto14 ch 1 l/bsto3 ch 0 l/bsto7 ch 1 l/bsto11 ch 1 l/bsto15 ch 1 l/bsto19 ch 1 l/bsto23 ch 1 l/bsto27 ch 1 l/bsto31 ch 2 l/bsto3 ch 0 l/bsto7 ch 0 l/bsto11 ch 0 l/bsto15 ch 0 l/bsto19 ch 0 l/bsto23 ch 0 l/bsto27 ch 0 l/bsto31 ch 1 l/bsto3 ch 0 l/bsto7 ch 1 l/bsto11 ch 1 l/bsto15 l/bcsto1 l/bcsto2 l/bcsto3 one c16o period channel 0 channel 255 1
zl50060/1 data sheet 38 zarlink semiconductor inc. 4.2 lors/bors asserted low, 32mbps mode note that when the devices are operating in local or backplane 32mbps mode, some of the output streams (the upper half of the available streams) are unused. the le/be bits of the channels on those output streams will always be low. therefore, the upper lsto/bsto pins are either driven high or high impedance, in accordance with the value of the lors/bors input signals, as shown in table 2 on page 33. the data (channel control bit) transmitted by l / bcsto0-3 replicates the local/backplane output enable ( le/be ) bit of the local/backplane connection memory, with a low state indicating the channel to be set to high impedance. refer to ?local connection memory bit definition,? on page 52 and ?backplane connection memory bit definition,? on page 53 for more details. the l/bcsto0-3 pins transmit serial data (channel control bits) at 16.384mbps, with each bit representing the per-channel high impedance state for a specific stream. four output streams are allocated to each control line as follows: ? l/bcsto0 outputs the channel control bits for streams l/bsto0, 4, 8, and 12 ? l/bcsto1 outputs the channel control bits for streams l/bsto1, 5, 9, and 13 ? l/bcsto2 outputs the channel control bits for streams l/bsto2, 6, 10, and 14 ? l/bcsto3 outputs the channel control bits for streams l/bsto3, 7, 11, and 15 the channel control bit location, within a frame period, for each channel of the local/backplane output streams is presented in table 4, l/bcsto allocation of channel control bits to output streams (32mbps mode) the l/bcsto0-3 pins output data at a constant data rate of 16.384mbps and all output streams, l/bsto0-15 , operate at a data rate of 32.768mbps. as an aid to the description, the channel control bit for a single channel on specific streams is presented, with reference to table 4: 1. the channel control bit corresponding to stream 0, channel 0, l/bsto0_ch0, is transmitted on l/bcsto0 and is advanced, relative to the frame boundary, by ten periods (clock period number 2039) of c16o . 2. the channel control bit corresponding to stream 12, channel 0, l/bsto12_ch0, is transmitted on l/bcsto0 in advance of the frame boundary by seven periods (clock period number2042) of output clock, c16o . similarly, the channel control bits for l/bsto13_ch0 , l/bsto14_ch0 and l/bsto15_ch0 are advanced relative to the frame boundary by seven periods of c16o , on l/bcsto1 , l/bcsto2 and l/bcsto3 , respectively. 3. for stream l/bsto4, the value of the channel control bit for channel 511 will be transmitted during the c16o clock period number 2036 on l/bcsto0 . 4. for stream l/bsto5, the value of the channel control bit for channel 5 will be transmitted during the c16o clock period number 12 on l/bcsto1 .
zl50060/1 data sheet 39 zarlink semiconductor inc. allocated stream no. channel no. 2 c16o period 1 l/bcsto0 l/bcsto1 l/bcsto2 l/bcsto3 32mbps 2039 0 3-1 123ch 0 20404567ch 0 2041 8 9 10 11 ch 0 2042 12 3-2 13 3-2 14 3-2 15 3-2 ch 0 20430123ch 1 20444567ch 1 2045 8 9 10 11 ch 1 2046 12 13 14 15 ch 1 20470123ch 2 20484567ch 2frame 1 8 9 10 11 ch 2 boundary 212131415 ch 2 30123ch 3 44567ch 3 58 91011ch 3 612131415 ch 3 70123ch 4 84567ch 4 98 91011ch 4 10 12 13 14 15 ch 4 110123ch 5 12 4 5 3-4 67ch 5 13 8 9 10 11 ch 5 14 12 13 14 15 ch 5 150123ch 6 164567ch 6 17 8 9 10 11 ch 6 etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. etc. 2029 etc. etc. etc. etc. ch 509 2030 12 13 14 15 ch 509 20310123ch 510 2032 4 5 6 7 ch 510 2033 8 9 10 11 ch 510 2034 12 13 14 15 ch 510 table 4 - l/bcsto allocation of channel control bits to output streams (32mbps mode)
zl50060/1 data sheet 40 zarlink semiconductor inc. note 1: clock period count is referenced to frame boundary. note 2: the channel numbers presented relate to the specific stream operating at a data rate of 32.768mbps. note 3: 3-1 to 3-4: see above for examples of channel control bits. 20350123ch 511 2036 4 3-3 567ch 511 2037 8 9 10 11 ch 511 2038 12 13 14 15 ch 511 20390123ch 0 20404567ch 0 2041 8 9 10 11 ch 0 2042 12 13 14 15 ch 0 20430123ch 1 20444567ch 1 2045 8 9 10 11 ch 1 2046 12 13 14 15 ch 1 20470123ch 2 20484567ch 2frame 1 8 9 10 11 ch 2 boundary 212131415 ch 2 30123ch 3 etc. etc. etc. etc. etc. etc. allocated stream no. channel no. 2 c16o period 1 l/bcsto0 l/bcsto1 l/bcsto2 l/bcsto3 32mbps table 4 - l/bcsto allocation of channel control bits to output streams (32mbps mode) (continued)
zl50060/1 data sheet 41 zarlink semiconductor inc. figure 14, local and backplane port external high impedance control timing (32mbps mode) shows the channel control bits for l/bcsto0 , l/bcsto1 , l/bcsto2 and l/bcsto3 . figure 14 - local and backplane port external high impedance control timing (32mbps mode) 4.3 lors/bors asserted high when the lors/bors input pin is high, the local/backplane output enable bit ( le/be ) of the local/backplane connection memory has direct per-channel control on the high impedance state of the local/backplane output streams, l/bsto0-31 . programming a low state in the connection memory le/be bit will set the stream output of the device to high impedance for the duration of the channel period. see ?local connection memory bit definition,? on page 52 and ?backplane connection memory bit definition,? on page 53 for programming details. when the lors/bors signal is asserted high, the l/bcsto0-3 outputs directly the values given in le/be. l/bcsto0 l/bsto0 (32mbps) c8o fp8o ch 2 l/bsto0 ch 2 l/bsto4 ch 2 l/bsto8 ch 2 l/bsto12 ch 3 l/bsto0 ch 3 l/bsto4 ch 3 l/bsto8 ch 3 l/bsto12 ch 4 l/bsto0 ch 4 l/bsto4 ch 0 l/bsto8 ch 0 l/bsto12 ch 1 l/bsto0 ch 1 l/bsto4 ch 1 l/bsto8 ch 1 l/bsto12 ch 2 l/bsto0 ch 2 l/bsto4 ch 2 l/bsto8 ch 2 l/bsto12 ch 2 l/bsto1 ch 2 l/bsto5 ch 2 l/bsto9 ch 2 l/bsto13 ch 3 l/bsto1 ch 3 l/bsto5 ch 3 l/bsto9 ch 3 l/bsto13 ch 4 l/bsto1 ch 4 l/bsto5 ch 0 l/bsto9 ch 0 l/bsto13 ch 1 l/bsto1 ch 1 l/bsto5 ch 1 l/bsto9 ch 1 l/bsto13 ch 2 l/bsto1 ch 2 l/bsto5 ch 2 l/bsto9 ch 2 l/bsto13 ch 2 l/bsto2 ch 2 l/bsto6 ch 2 l/bsto10 ch 2 l/bsto14 ch 3 l/bsto2 ch 3 l/bsto6 ch 3 l/bsto10 ch 3 l/bsto14 ch 4 l/bsto2 ch 4 l/bsto6 ch 0 l/bsto10 ch 0 l/bsto14 ch 1 l/bsto2 ch 1 l/bsto6 ch 1 l/bsto10 ch 1 l/bsto14 ch 2 l/bsto2 ch 2 l/bsto6 ch 2 l/bsto10 ch 2 l/bsto14 ch 2 l/bsto3 ch 2 l/bsto7 ch 2 l/bsto11 ch 2 l/bsto15 ch 3 l/bsto3 ch 3 l/bsto7 ch 3 l/bsto11 ch 3 l/bsto15 ch 4 l/bsto3 ch 4 l/bsto7 ch 0 l/bsto11 ch 0 l/bsto15 ch 1 l/bsto3 ch 1 l/bsto7 ch 1 l/bsto11 ch 1 l/bsto15 ch 2 l/bsto3 ch 2 l/bsto7 ch 2 l/bsto11 ch 2 l/bsto15 l/bcsto1 l/bcsto2 l/bcsto3 one c16o cycle l/bsto1 (32mbps) l/bsto2 (32mbs) l/bsto3 (32mbps) channel 511 bits 7-0 channel 510 bits 7-0 channel 511 bits 7-0 channel 510 bits 7-0 channel 511 bits 7-0 channel 510 bits 7-0 channel 511 bits 7-0 channel 510 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0 channel 1 bits 7-0 channel 0 bits 7-0
zl50060/1 data sheet 42 zarlink semiconductor inc. 5.0 data delay through the switching paths serial data which goes into the device is converted into parallel format and written to consecutive locations in the data memory. each data memory location corresponds to the input stream and channel number. with the input channel delay feature disabled, channels written to any of the buffers during frame n will be read out during frame n+2. with the input channel delay feature enabled, channels written to any of the buffers during frame n will be read out during frame n+3. the input channel offsets affect the overall throughput delay; however the input bit delay and output bit advancement have no impact on the overall data throughput delay. in the following paragraphs, the data throughput delay ( t ) is represented as a function of st-bus frames, input channel number, ( m ), output channel number ( n ), and input channel delay ( ). table 5 describes the variable range for input streams and table 6 describes the variable range for output streams. table 7 summarizes the data throughput delay under various input channel and output channel delay conditions. input stream data rate input channel number (m) possible input channel delay ( ) 2mbps 0 to 31 0 to 31 4mbps 0 to 63 0 to 63 8mbps 0 to 127 0 to 127 16mbps 0 to 255 0 to 255 32mbps 0 to 511 0 to 511 table 5 - variable range for input streams output stream data rate output channel number (n) 2mbps 0 to 31 4mbps 0 to 63 8mbps 0 to 127 16mbps 0 to 255 32mbps 0 to 511 table 6 - variable range for output streams input channel delay off input channel delay on t = 2 frames + (n - m) t = 3 frames - + (n - m) table 7 - data throughput delay
zl50060/1 data sheet 43 zarlink semiconductor inc. by default, when the input channel delay, , is set to zero, the data throughput delay ( t ) is: t = 2 frames + (n - m) . assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is exactly 2 frames. figure 15 - data throughput delay with input channel delay disabled, input ch0 switched to output ch0 assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read exceeds 2 frames. figure 16 - data throughput delay with input channel delay disabled, input ch0 switched to output ch13 assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read is less than 2 frames. figure 17 - data throughput delay with input channel delay disabled, input ch13 switched to output ch0 frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data (no delay) serial output data (no delay) frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + 0 frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data (no delay) serial output data (no delay) frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + (n - m) frame frame n frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 frame n data frame n+1data frame n+2 data frame n+3 data frame n+4 data frame n+5 data serial input data (no delay) serial output data (no delay) frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n+3 data 2 frames + (n - m)
zl50060/1 data sheet 44 zarlink semiconductor inc. when the input channel delay, , is enabled, the data throughput delay is: t = 3 frames - + (m - n) . assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is less than 3 frames. figure 18 - data throughput delay with input channel delay enabled, input ch0 switched to output ch0 assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read could exceed 3 frames, if the distance between n and m is greater than the input channel delay. figure 19 - data throughput delay with input channel delay enabled, input ch0 switched to output ch13 assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read will be less than 3 frames. figure 20 - data throughput delay with input channel delay enabled, input ch13 switched to output ch0 frame frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 serial output data frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data serial input data ( > 0) frame n-1 data frame n+4 data frame n input channel delay (from 1 to max # of channels) 3 frames - + 0 frame frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 serial output data frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data serial input data ( > 0) frame n-1 data frame n+4 data frame n input channel delay (from 1 to max # of channels) 3 frames - + (n - m) frame frame n+1 frame n+2 frame n+3 frame n+4 frame n+5 serial output data frame n-3 data frame n-2 data frame n-1 data frame n data frame n+1 data frame n+2 data frame n data frame n+1 data frame n+2 data frame n+3 data frame n+4 data serial input data ( > 0) frame n-1 data frame n+4 data frame n input channel delay (from 1 to max # of channels) 3 frames - + (n - m)
zl50060/1 data sheet 45 zarlink semiconductor inc. 6.0 bit error rate test independent bit error rate (ber) testers are provided for the local and backplane ports. in both ports there is a ber transmitter and a ber receiver. the transmitter and receiver are each independently controlled to allow backplane-to-backplane, local-to-local, backplane-to-local or local-to-backplane testing. the transmitter generates a 2 15 -1 or 2 23 -1 pseudo random binary sequence (prbs), which may be allocated to a specific stream and number of channels. this is defined by a stream number, a start channel number, and the number of consecutive channels following the start channel. the stream, channel number and the number of consecutive channels following the start channel are similarly allocated for the receiver and detection of the prbs. examples of a channel sequence are presented in figure 21. figure 21 - examples of ber transmission channels on a 16mbps output stream when enabled, the receiver attempts to lock to the prbs on the incoming bit stream. once lock is achieved, by detection of a seed value, a bit-by-bit comparison takes place and each error will increment a 16-bit counter. a counter saturation to ffff h occurs in the event of an error count in excess of 65,535. the ber operations are controlled by registers as follows (refer to section 14.3, bit error rate test control register (bercr) for overall control, section 14.10, local bit error rate (ber) registers and section 14.11, backplane bit error rate (ber) registers for register programming details): ? ber control register ( bercr ) - independently enables ber transmission and receive testing for backplane and local ports. ? local and backplane ber start send registers ( lbssr and bbssr ) - define the output stream and start channel for ber transmission. ? local and backplane transmit ber length registers ( ltxblr and btxblr ) - define, for transmit stream, how many consecutive channels to follow the start channel. ? local and backplane ber start receive registers ( lbsr and bbsr ) - define the input stream and channel from which the ber sequence will start to be compared. ? local and backplane receive ber length registers ( lrxblr and brxblr ) - define, for the receive stream, how many consecutive channels to follow the start channel. ? local and backplane ber count registers ( lbcr and bbcr ) - contain the number of counted errors. the registers listed completely define the transmit and receive stream and channels. when ber transmission is enabled for these channels, the source bits and the message mode bits, lsrc and lmm in the local connection memory, and bsrc and bmm in the backplane connection memory, are ignored. the per-channel enable bits ( le 0 1 2 ...... ..... 254 3 ..... ..... 255 0 1 2 ...... ..... 254 3 ..... ..... 255 0 1 2 ...... ..... 254 3 ..... ..... 255 0 1 channels containing unknown data channels containing prbs sequence start ch=0 l/btxb8-0=111111111 b start ch=0 l/bxtr8-0=000000001 b start ch=254 l/bxtr8-0=000000011 b 0 0 1 1 fp8i once started, ber transmission continues until stopped by the ber control register. 2 2 2 note: total length = number of consecutive channels desired programmed in l/btxr8-0 - 1 channel frame boundary total length = 256 channels total length = 3 channels total length = 4 channels
zl50060/1 data sheet 46 zarlink semiconductor inc. and be ) of the respective connection memories should be set to high to enable the outputs for the selected channels. the ber receive channel numbering is not affected by the input channel delay value. it means that the ber receive circuitry always assume there is no input channel delay, regardless of the values of the bcdr and lcdr registers. for example, if ber data is received on local input stream 0 channel 3, without input channel delay, the lbsrr (local ber start receive register) should be programmed to 3. with input channel delay of 5, however, the lbsrr should be programmed to 8 (3 + 5) instead. note that when ber transmission is enabled, the target channels will carry prbs data, and the rest of the channels on all streams of the same side (local/backplane) will carry unknown data, which renders that side of the switch unable to switch traffic during ber test. 7.0 microprocessor port the 16k switch family supports non-multiplexed motorola type microprocessor buses. the microprocessor port consists of a 16-bit parallel data bus ( d0-15 ), a 15-bit address bus ( a0-14 ) and four control signals ( cs , ds , r/w and dta ). the data bus provides access to the internal registers, the backplane connection and data memories, and the local connection and data memories. each memory has 8,192 locations. see table 11, address map for data and connection memory locations (a14 = 1), for the address mapping. each connection memory can be read or written via the 16-bit microprocessor port. the data memories can only be read (but not written) from the microprocessor port. to prevent the bus ?hanging?, in the event of the switch not receiving a master clock, the microprocessor port shall complete the dta handshake when accessed, but any data read from the bus will be invalid. 8.0 device power-up, initialization and reset 8.1 power-up sequence the recommended power-up sequence is for the v dd_io supply (nominally +3.3v) to be established before the power-up of the v dd_pll and v dd_core supplies (nominally +1.8v). the v dd_pll and v dd_core supplies may be powered up simultaneously, but neither should 'lead' the v dd_io supply by more than 0.3v. all supplies may be powered-down simultaneously. 8.2 initialization upon power up, the device should be initialized by applying the following sequence: 1 ensure the trst pin is permanently low to disable the jtag tap controller. 2set ode pin to low. this configures the lcsto0-3 output signals to low (i.e., setting optional external output buffers to high impedance), and sets the lsto0-31 outputs to high or high impedance, dependent on the lors input value, and sets the bcsto0-3 output signals to low (i.e. setting optional external output buffers to high impedance), and sets the bsto0-31 outputs to high or high impedance, dependent on bors input value. refer to pin description for details of the lors and bors pins. 3 reset the device by asserting the reset pin to zero for at least two cycles of the input clock, c8i . a delay of an additional 250 s must also be applied before the first microprocessor access is performed following the de-assertion of the reset pin; this delay is required for determination of the input frame pulse format.
zl50060/1 data sheet 47 zarlink semiconductor inc. 8.3 reset the reset pin is used to reset the device. when set low, an asynchronous reset is applied to the device. it is then synchronized to the internal clock. during the reset period, depending on the state of input pins lors and bors , the output streams lsto0-31 and bsto0-31 are set to high or high impedance, and all internal registers and counters are reset to the default state. the reset pin must remain low for two input clock cycles ( c8i ) to guarantee a synchronized reset release. a delay of an additional 250 s must also be waited before the first microprocessor access is performed following the de-assertion of the reset pin; this delay is required for determination of the frame pulse format. in addition, the reset signal must be de-asserted less than 12 s after the frame boundary or more than 13 s after the frame boundary, as illustrated in figure 22. this can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse fp8i . figure 22 - hardware reset de-assertion 9.0 connection memory the device includes two connection memories, the local connection memory and the backplane connection memory. 9.1 local connection memory the local connection memory (lcm) is a 16-bit wide memory with 8,192 memory locations to support the local output port. the most significant bit of each word, bit[15], selects the source stream from either the backplane (lsrc = low) or the local (lsrc = high) port and determines the backplane-to-local or local-to-local data routing. bits[14:13] select the control modes of the local output streams, the per-channel message mode and the per-channel high impedance output control modes. in connection mode (bit[14] = low), bits[12:0] select the source stream and channel number as detailed in table 8. in message mode (bit[14] = high), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. bit[13] must be high for message mode to ensure that the output channel is not tri-stated. 4 use the block programming mode to initialize the local and the backplane connection memories. refer to section 9.3, connection memory block programming. 5set ode pin to high after the connection memories are programmed to ensure that bus contention will not occur at the serial stream outputs. fp8i reset 12 s 13 s de-assertion of reset must not fall within this window reset assertion reset de-assertion reset (case 1) (case 2)
zl50060/1 data sheet 48 zarlink semiconductor inc. 9.2 backplane connection memory the backplane connection memory (bcm) is a 16-bit wide memory with 8,192 memory locations to support the backplane output port. the most significant bit of each word, bit[15], selects the source stream from either the backplane (bsrc = high) or the local (bsrc = low) port and determines the local-to-backplane or backplane-to-backplane data routing. bit[14:13] select the control modes of the backplane output streams, namely the per-channel message mode and the per-channel high impedance output control mode. in connection mode (bit[14] = low), bits[12:0] select the source stream and channel number as detailed in table 8. in message mode (bit[14] = high), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. bit[13] must be high for message mode to ensure that the output channel is not tri-stated. the control register bits ms[2:0] must be set to 000 to select the local connection memory for the write and read operations via the microprocessor port. the control register bits ms[2:0] must be set to 001 to select the backplane connection memory for the write and read operations via the microprocessor port. see section 7.0, microprocessor port, and section 14.1, control register (cr) for details on microprocessor port access. 9.3 connection memory block programming this feature allows fast, simultaneous, initialization of the local and backplane connection memories after power-up. when the memory block programming mode is enabled, the contents of the block programming register (bpr) will be loaded into the connection memories. see table 19 and table 20 for details of the control register and block programming register values, respectively. 9.3.1 memory block programming procedure: ? set the mbp bit in the control register from low to high. ?set the bpe bit to high in the block programming register (bpr). the local block programming data bits, lbpd[2:0] , of the block programming register, will be loaded into bits[15:13] of the local connection memory. the remaining bit positions are loaded with zeros as shown in table 9. source stream bit rate source stream no. source channel no. 2mbps bits[12:8] legal values 0:31 bits[7:0] legal values 0:31 4mbps bits[12:8] legal values 0:31 bits[7:0] legal values 0:63 8mbps bits[12:8] legal values 0:31 bits[7:0] legal values 0:127 16mbps bits[12:8] legal values 0:31 bits[7:0] legal values 0:255 32mbps bits[12:9] legal values 0:15 bits[8:0] legal values 0:511 table 8 - local and backplane connection memory configuration 15 14 13 1211109876543210 lbpd2 lbpd1lbpd00000000000000 table 9 - local connection memory in block programming mode
zl50060/1 data sheet 49 zarlink semiconductor inc. the backplane block programming data bits, bbpd[2:0] , of the block programming register, will be loaded into bits[15:13] respectively, of the backplane connection memory. the remaining bit positions are loaded with zeros as shown in table 10. the block programming register bit, bpe will be automatically reset low within 125 s, to indicate completion of memory programming. the block programming mode can be terminated at any time prior to completion by clearing the bpe bit of the block programming register or the mbp bit of the control register. note that the default values (low) of lbpd[2:0] and bbpd[2:0] of the block programming register, following a device reset, can be used. during reset, all output channels go high or high impedance, depending on the value of the lors and bors pins, irrespective of the values in bits[14:13] of the connection memory. 10.0 memory built-in-self-test (bist) mode as operation of the memory bist will corrupt existing data, this test must only be initiated when the device is placed ?out-of-service? or isolated from live traffic. the memory bist mode is enabled through the microprocessor port ( section 14.14, memory bist register ). internal bist memory controllers generate the memory test pattern (s-march) and control the memory test. the memory test result is monitored through the memory bist register. 11.0 jtag port the zl50060/1 jtag interface conforms to the ieee 1149.1 standard. the operation of the boundary-scan circuit shall be controlled by an external test access port (tap) controller. 11.1 test access port (tap) the test access port (tap) consists of four input pins and one output pin described as follows: ? test clock input (tck) tck provides the clock for the tap controller and is independent of any on-chip clock. tck permits the shifting of test data into or out of the boundary-scan register cells under the control of the tap controller in boundary-scan mode. ? test mode select input (tms) the tap controller uses the logic signals applied to the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin in internally pulled to v dd_io when not driven from an external source. ? test data input (tdi) depending on the previously applied data to the tms input, the serial input data applied to the tdi port is connected either to the instruction register or to a test data register. both registers are described in section 11.2, tap registers. the applied input data is sampled at the rising edge of tck pulses. this pin is internally pulled to v dd_io when not driven from an external source. ? test data output (tdo) depending on the previously applied sequence to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo . the data out of the tdo is clocked on the 15 14 13 1211109876543210 bbpd2bbpd1bbpd0 0000000000000 table 10 - backplane connection memory in block programming mode
zl50060/1 data sheet 50 zarlink semiconductor inc. falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo output is set to a high impedance state. ? test reset (trst ) trst provides an asynchronous reset to the jtag scan structure. this pin is internally pulled high when not driven from an external source. this pin must be pulled low for normal operation. 11.2 tap registers the zl50060/1 implements the public instructions defined in the ieee-1149.1 standard with the provision of an instruction register and three test data registers. 11.2.1 test instruction register the jtag interface contains a four-bit instruction register. instructions are serially loaded into the instruction register from the tdi pin when the tap controller is in the shift-ir state. instructions are subsequently decoded to achieve two basic functions: to select the test data register to operate while the instruction is current, and to define the serial test data register path to shift data between tdi and tdo during data register scanning. please refer to figure 34 for jtag test port timing. 11.2.2 test data registers 11.2.2.1 the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the zl50060/1 core logic. 11.2.2.2 the bypass register the bypass register is a single stage shift register to provide a one-bit path from tdi to tdo . 11.2.2.3 the device identification register the jtag device id for the zl50060/1 is 0c38d14b h . version, bits <31:28>:0000 part no., bits <27:12>:1100 0011 1000 1101 manufacturer id, bits <11:1>:0001 0100 101 header, bit <0> (lsb):1 11.3 boundary scan description language (bsdl) file a boundary scan description language (bsdl) file is available from zarlink semiconductor to aid in the use of the ieee 1149.1 test interface.
zl50060/1 data sheet 51 zarlink semiconductor inc. 12.0 memory address mappings when the most significant bit, a14, of the address bus is set to ?1?, the microprocessor performs an access to one of the device?s internal memories. the control register bits ms[2:0] indicate which memory (local connection, local data, backplane connection, or backplane data) is being accessed. address bits a0-a13 indicate which location within the particular memory is being accessed. table 11 - address map for data and connection memory locations (a14 = 1) the device contains two data memory blocks, one for received backplane data and one for received local data. for all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the relevant data memory. 12.1 local data memory bit definition the 8-bit local data memory (ldm) has 8,192 positions. the locations are associated with the local input streams and channels. as explained in the section above, address bits a13-a0 of the microprocessor define the addresses of the streams and the channels. the ldm is read-only and configured as follows: table 12 - local data memory (ldm) bits note that the local data memory is actually an 8-bit wide memory. the most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. address bit description a14 selects memory or register access (0 = register, 1 = memory). note that which memory (local connection, local data, backplane connection, backplane data) is accessed depends on the ms[2:0] bits in the control register . a13-a9 stream address (0 - 31) only streams 0 to 15 are used when the target side (local/backplane) is operating at 32.768mbps. a8-a0 channel address (0 - 511) channels 0 to 31 are used when serial stream is at 2.048mbps channels 0 to 63 are used when serial stream is at 4.096mbps channels 0 to 127 are used when serial stream is at 8.192mbps channels 0 to 255 are used when serial stream is at 16.384mbps channels 0 to 511 are used when serial stream is at 32.768mbps bit name description 15:8 reserved set to a default value of 8?h00. 7:0 ldm local data memory - local input channel data. the ldm[7:0] bits contain the timeslot data from the local side input tdm stream. ldm[7] corresponds to the first bit received, i.e. bit 7 in st-bus mode, bit 0 in gci-bus mode. see figure 7, st-bus and gci-bus input timing diagram for different data rates for the arrival order of the bits.
zl50060/1 data sheet 52 zarlink semiconductor inc. 12.2 backplane data memory bit definition the 8-bit backplane data memory (bdm) has 8,192 positions. the locations are associated with the backplane input streams and channels. as explained previously, address bits a13-a0 of the microprocessor define the addresses of the streams and the channels. the bdm is read-only and configured as follows: table 13 - backplane data memory (bdm) bits note that the backplane data memory is actually an 8-bit wide memory. the most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. 12.3 local connection memory bit definition the local connection memory (lcm) has 8,192 addresses of 16-bit words. each address, accessed through bits a13-a0 of the microprocessor port, is allocated to an individual local output stream and channel. the bit definition for each 16-bit word is presented in table 14 for non-32mbps source-to-local mode connections, and in table 15 for 32mbps source-to-local mode connections. the most-significant bit in the memory location, lsrc, selects the switch configuration for backplane-to-local or local-to-local. when the per-channel message mode is selected (lmm memory bit = high), the lower byte of the lcm word (lcab[7:0]) will be transmitted as data on the output stream (lsto0-31) in place of data defined by the source control, stream and channel address bits. . bit name description 15:8 reserved set to a default value of 8?h00. 7:0 bdm backplane data memory - backplane input channel data. the bdm[7:0] bits contain the timeslot data from the backplane side input tdm stream. bdm[7] corresponds to the first bit received, i.e. bit 7 in st-bus mode, bit 0 in gci-bus mode. see figure 7, st-bus and gci-bus input timing diagram for different data rates for the arrival order of the bits bit name description 15 lsrc local source control bit when low, the source is from the backplane input port (backplane data memory). when high, the source is from the local input port (local data memory). ignored when lmm is set high. 14 lmm local message mode bit when low, the channel is in connection mode (data to be output on channel originated in local or backplane data memory). when high, the channel is in message mode (data to be output on channel originated in local connection memory). 13 le local output enable bit when low, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the lors pin. when high, the channel is active. 12:8 lsab[4:0] source stream address bits the binary value of these 5 bits represents the input stream number. ignored when lmm is set high. table 14 - lcm bits for non-32mbps source-to-local switching
zl50060/1 data sheet 53 zarlink semiconductor inc. table 15 - lcm bits for 32mbps source-to-local switching 12.4 backplane connection memory bit definition the backplane connection memory (bcm) has 8,192 addresses of 16-bit words. each address, accessed through bits a13-a0 of the microprocessor port, is allocated to an individual backplane output stream and channel. the bit definition for each 16-bit word is presented in table 16 for non-32mbps source-to-backplane mode connections, and in table 17 for 32mbps source-to-backplane mode connections. the most-significant bit in the memory location, bsrc, selects the switch configuration for local-to-backplane or backplane-to-backplane. when the per-channel message mode is selected (bmm memory bit = high), the lower byte of the bcm word (bcab[7:0]) will be transmitted as data on the output stream (bsto0-31) in place of data defined by the source control, stream and channel address bits. 7:0 lcab[7:0] source channel address bits / message mode data the binary value of these 8 bits represents the input channel number when lmm is set low. transmitted as data when lmm is set high. note: when lmm is set high, in both st-bus and gci-bus modes, the lcab[7:0] bits are output sequentially to the timeslot with lcab[7] being output first. bit name description 15 lsrc local source control bit when low, the source is from the backplane input port (backplane data memory). when high, the source is from the local input port (local data memory). ignored when lmm is set high. 14 lmm local message mode bit when low, the channel is in connection mode (data to be output on channel originated in local or backplane data memory). when high, the channel is in message mode (data to be output on channel originated in local connection memory). 13 le local output enable bit when low, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the lors pin. when high, the channel is active. 12:9 lsab[3:0] source stream address bits the binary value of these 4 bits represents the input stream number. ignored when lmm is set high. 8:0 lcab[8:0] source channel address bits / message mode data the binary value of these 9 bits represents the input channel number, when lmm is low. bits lcab[7:0] transmitted as data when lmm is set high. note: when lmm is set high, in both st-bus and gci-bus modes, the lcab[7:0] bits are output sequentially to the timeslot with lcab[7] being output first. bit name description table 14 - lcm bits for non-32mbps source-to-local switching (continued)
zl50060/1 data sheet 54 zarlink semiconductor inc. . table 16 - bcm bits for non-32mbps source-to-backplane switching bit name description 15 bsrc backplane source control bit when low, the source is from the local input port (local data memory). when high, the source is from the backplane input port (backplane data memory). ignored when bmm is set high. 14 bmm backplane message mode bit when low, the channel is in connection mode (data to be output on channel originated in backplane or local data memory). when high, the channel is in message mode (data to be output on channel originated in backplane connection memory). 13 be backplane output enable bit when low, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the bors pin. when high, the channel is active. 12:8 bsab[4:0] source stream address bits the binary value of these 5 bits represents the input stream number. ignored when bmm is set high. 7:0 bcab[7:0] source channel address bits / message mode data the binary value of these 8 bits represents the input channel number when bmm is set low. transmitted as data when bmm is set high. note: when bmm is set high, in both st-bus and gci-bus modes, the bcab[7:0] bits are output sequentially to the timeslot with bcab[7] being output first. bit name description 15 bsrc backplane source control bit when low, the source is from the local input port (local data memory). when high, the source is from the backplane input port (backplane data memory). ignored when bmm is set high. 14 bmm backplane message mode bit when low, the channel is in connection mode (data to be output on channel originated in backplane or local data memory). when high, the channel is in message mode (data to be output on channel originated in backplane connection memory). 13 be backplane output enable bit when low, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the bors pin. when high, the channel is active. 12:9 bsab[3:0] source stream address bits the binary value of these 4 bits represents the input stream number. ignored when bmm is set high.
zl50060/1 data sheet 55 zarlink semiconductor inc. table 17 - bcm bits for 32mbps source-to-backplane switching 13.0 internal register mappings when the most significant bit, a14, of the address bus is set to ?0?, the microprocessor is performing an access to one of the device?s internal registers. address bits a13-a0 indicate which particular register is being accessed. 8:0 bcab[8:0] source channel address bits / message mode data the binary value of these 9 bits represents the input channel number, when bmm is low. bits bcab[7:0] transmitted as data when bmm is set high. note: when bmm is set high, in both st-bus and gci-bus modes, the bcab[7:0] bits are output sequentially to the timeslot with bcab[7] being output first. a14-a0 register 0000 h control register, cr 0001 h block programming register, bpr 0002 h ber control register, bercr 0003 h - 0022 h local input channel delay register 0 - 31, lcdr0 - 31 0023 h - 0042 h local input bit delay register 0 - 31, lidr0 - 31 0043 h - 0062 h backplane input channel delay register 0 - 31, bcdr0 - 31 0063 h - 0082 h backplane input bit delay register 0 - 31, bidr0 - 31 0083 h - 00a2 h local output advancement register 0 - 31, loar0 - 31 00a3 h - 00c2 h backplane output advancement register 0 - 31, boar0 - 31 00c3 h local ber start send register, lbssr 00c4 h local transmit ber length register, ltxblr 00c5 h local receive ber length register, lrxblr 00c6 h local ber start receive register, lbsrr 00c7 h local ber count register, lbcr 00c8 h backplane ber start send register, bbssr 00c9 h backplane transmit ber length register, btxblr 00ca h backplane receive ber length register, brxblr 00cb h backplane ber start receive register, bbsrr 00cc h backplane ber count register, bbcr 00cd h - 00ec h local input bit rate register 0 - 31, librr0 - 31 00ed h - 010c h local output bit rate register 0 - 31, lobrr0 - 31 010d h - 012c h backplane input bit rate register 0 - 31, bibrr0 - 31 table 18 - address map for registers (a14 = 0) bit name description
zl50060/1 data sheet 56 zarlink semiconductor inc. 14.0 detailed register descriptions this section describes the registers that are used in the device. 14.1 control register (cr) address 0000 h . the control register defines which memory is to be accessed. it initiates the memory block programming mode and selects the backplane and local data rate modes. the control register ( cr ) is configured as follows: 012d h - 014c h backplane output bit rate register 0 - 31, bobrr0 - 31 014d h memory bist register, mbistr 3fff h device identification register, dir bit name reset value description 15:13 fbd_ mode[2:0] 0 frame boundary discriminator mode when set to 111 b , the frame boundary discriminator can handle both low frequency and high frequency jitter. when set to 000 b , the frame boundary discriminator is set to handle lower frequency jitter only. all other values are reserved. these bits are ignored when fbden bit is low. 12 smpl_ mode 0 sample point mode when low the input bit sampling point is always at the 3/4 bit location. the input bit fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value of the lidr0 to lidr31 and bidr0 to bidr31 registers. when high, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit location as per the value of the lidr0 to lidr31 and bidr0 to bidr31 registers. in addition, the incoming data can be delayed by 0 to 7 bits in 1 bit increments. see table 24, table 25, table 28 and table 29 for details. 11 reserved 0 reserved must be set to 0 for normal operation 10 fbden 0 frame boundary discriminator enable when low, the frame boundary discriminator function is disabled. when high, enables frame boundary discriminator function which allows the device to tolerate inconsistent frame boundaries, hence improving the tolerance to cycle-to-cycle variation on the input clock. 9mode32l0 local 32mhz mode when low, local streams lsti0-31 and lsto0-31 can be individually programmed for data rates of 2, 4, 8, or 16mbps. when high, local streams lsti0-15 and lsto0-15 operate at 32.768mbps only and lsti16-31 and lsto16-31 are unused. table 19 - control register bits a14-a0 register table 18 - address map for registers (a14 = 0) (continued)
zl50060/1 data sheet 57 zarlink semiconductor inc. 8fpw 0 frame pulse width when low, the user must apply a 122ns frame pulse on fp8i ; the fp8o pin will output a 122ns wide frame pulse; fp16o will output a 61ns wide frame pulse. when high, the user must apply a 244ns frame pulse on fp8i ; the fp8o pin will output a 244ns wide frame pulse; fp16o will output a 122ns wide frame pulse. 7 mode32b 0 backplane 32mhz mode when low, backplane streams bsti0-31 and bsto0-31 may be individually programmed for data rates of 2, 4, 8, or 16mbps. when high, backplane streams bsti0-15 and bsto0-15 operate at 32.768mbps only and bsti16-31 and bsto16-31 are unused. 6c8ipol 0 8mhz input clock polarity the frame boundary is aligned to the falling or rising edge of the input clock. when low, the frame boundary is aligned to the clock falling edge. when high, the frame boundary is aligned to the clock rising edge. 5 copol 0 output clock polarity when low, the output clock has the same polarity as the input clock. when high, the output clock is inverted. this applies to both the 8mhz (c8o ) and 16mhz (c16o ) output clocks. 4mbp 0 memory block programming when low, the memory block programming mode is disabled. when high, the connection memory block programming mode is ready to program the local connection memory (lcm) and the backplane connection memory (bcm). 3osb 0 output stand by this bit enables the bsto0-31 and lsto0-31 serial outputs . when low, bsto0-31 and lsto0-31 are driven high or high impedance, dependent on the bors and lors pin settings respectively, and bcsto0-3 and lcsto0-3 are driven low. when high, bsto0-31, lsto0-31, bcsto0-3 and lcsto0-3 are enabled. 2 reserved 0 reserved must be set to 0 for normal operation 1:0 ms[1:0] 0 memory select bits these three bits select the connection or data memory for subsequent microport memory access operations: 00 selects local connection memory (lcm) for read or write operations. 01 selects backplane connection memory (bcm) for read or write operations. 10 selects local data memory (ldm) for read-only operation. 11 selects backplane data memory (bdm) for read-only operation. bit name reset value description table 19 - control register bits (continued) output control with ode pin and osb bit ode pin osb bit bsto0-31, lsto0-31 0x disabled 10 disabled 1 1 enabled
zl50060/1 data sheet 58 zarlink semiconductor inc. figure 23 - frame boundary conditions, st-bus operation frame boundary c8i fp8i frame pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 0 (a) frame pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 1 (b) frame pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 0 (c) frame pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 1 (d) c8i fp8i c8i fp8i c8i fp8i
zl50060/1 data sheet 59 zarlink semiconductor inc. figure 24 - frame boundary conditions, gci-bus operation frame boundary pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 0 (e) pulse width = 122ns, control register bit8 (fpw) = 0 control register bit6 (c8ipol) = 1 (f) pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 0 (g) pulse width = 244ns, control register bit8 (fpw) = 1 control register bit6 (c8ipol) = 1 (h) c8i fp8i c8i fp8i c8i fp8i c8i fp8i
zl50060/1 data sheet 60 zarlink semiconductor inc. 14.2 block programming register (bpr) address 0001 h . the block programming register stores the bit patterns to be loaded into the connection memories when the memory block programming feature is enabled. the bpe, lbpd[2:0] and bbpd[2:0] bits in the bpr register must be defined in the same write operation. the bpe bit is set high to commence the block programming operation. programming is completed in one frame period and may be initiated at any time within a frame. the bpe bit returns to low to indicate that the block programming function has completed. when bpe is high, no other bits of the bpr register may be changed for at least a single frame period, except to abort the programming operation. the programming operation may be aborted by setting either bpe to low, or the control register bit, mbp, to low. the bpr register is configured as follows. . table 20 - block programming register bits bit name reset value description 15:7 reserved 0 reserved must be set to 0 for normal operation 6:4 bbpd[2:0] 0 backplane block programming data these bits refer to the value loaded into the backplane connection memory (bcm) when the memory block programming feature is activated. when the mbp bit in the control register (cr) is set high and bpe (in this register) is set high, the contents of bits bbpd[2:0] are loaded into bits 15-13, respectively, of the bcm. bits 12-0 of the bcm are set low. 3:1 lbpd[2:0] 0 local block programming data these bits refer to the value loaded into the local connection memory (lcm), when the memory block programming feature is activated. when the mbp bit in the control register is set high and bpe (in this register) is set high, the contents of bits lbpd[2:0] are loaded into bits 15-13, respectively, of the lcm. bits 12-0 of the lcm are set low. 0bpe 0 block programming enable a low to high transition of this bit enables the memory block programming function. a low will be returned after 125 s, upon completion of programming. set low to abort the programming operation.
zl50060/1 data sheet 61 zarlink semiconductor inc. 14.3 bit error rate test control register (bercr) address 0002 h . the ber test control register controls backplane and local port ber testing. it independently enables and disables transmission and reception. it is configured as follows: bit name reset value description 15:12 reserved 0 reserved must be set to 0 for normal operation 11 lockb 0 backplane lock (read only) this bit is automatically set high when the receiver has locked to the incoming data sequence. the bit is reset by a low to high transition on sberrxb. 10 prstb 0 pber reset for backplane a low to high transition initializes the backplane ber generator to the seed value. 9 cberb 0 clear bit error rate register for backplane a low to high transition in this bit resets the backplane internal bit error counter and the backplane bit error register (bberr) to zero. 8sberrxb0 start bit error rate receiver for backplane a low to high transition enables the backplane ber receiver. the receiver monitors incoming data for reception of the seed value. when detected, the lock state is indicated (lockb), the receiver compares the incoming bits with the reference generator for bit equality, and increments the backplane bit error register (bbcr) on each failure. when low, bit comparison is disabled and the error count is frozen. 7sbertxb0 start bit error rate transmitter for backplane a low to high transition starts the ber transmission on the backplane. when low, backplane transmission is disabled. 6prbsb0 ber mode select for backplane when high, a prbs sequence of length 2 23 -1 is selected for the backplane port. when low, a prbs sequence of length 2 15 -1 is selected for the backplane port. 5lockl0 local lock (read only) this bit is automatically set high when the receiver has locked to the incoming data sequence. the bit is reset by a low to high transition on sberrxl 4prstl0 pber reset for local a low to high transition initializes the local ber generator to the seed value. 3cberl0 clear bit error rate register for local a low to high transition resets the local internal bit error counter and the local bit error register (lberr) to zero. table 21 - bit error rate test control register (bercr) bits
zl50060/1 data sheet 62 zarlink semiconductor inc. 14.4 local input channel delay registers (lcdr0 to lcdr31) addresses 0003h to 0022 h . thirty-two local input channel delay registers (lcdr0 to lcdr31) allow users to program the input channel delay for the local input data streams lsti0-31. the maximum possible adjustment is 511 channels and the lcdr0 to lcdr31 registers are configured as follows: : table 22 - local input channel delay register (lcdrn) bits 2 sberrxl 0 start bit error rate receiver for local a low to high transition enables the local ber receiver. the receiver monitors incoming data for reception of the seed value. when detected, the lock state is indicated (lockl), the receiver compares the incoming bits with the reference generator for bit equality, and increments the local bit error register (lbcr) on each failure. when low, bit comparison is disabled and the error count is frozen. 1 sbertxl 0 start bit error rate transmitter for local a low to high transition enables the local ber transmission. when low, local transmission is disabled. 0prbsl0 ber mode select for local when high, a prbs sequence of length 2 23 -1 is selected for the local port. when low, a prbs sequence of length 2 15 -1 is selected for the local port. lcdrn bit (where n = 0 to 31 for local non-32mbps mode, n = 0 to 15 for local 32mbps mode) name reset value description 15:9 reserved 0 reserved must be set to 0 for normal operation 8:0 lcd[8:0] 0 local channel delay register the binary value of these bits refers to the channel delay value for the local input stream. bit name reset value description table 21 - bit error rate test control register (bercr) bits (continued)
zl50060/1 data sheet 63 zarlink semiconductor inc. 14.4.1 local channel delay bits 8-0 (lcd8 - lcd0) these nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the local input pins. the input channel delay can be selected to be up to 511 (32mbps streams), 255 (16mbps streams), 127 (8mbps streams), 63 (4mbps streams) or 31 (2mbps streams) channels from the frame boundary. input stream channel delay corresponding delay bits lcd8-lcd0 0 channel (default) 0 0000 0000 1 channel 0 0000 0001 2 channels 0 0000 0010 3 channels 0 0000 0011 4 channels 0 0000 0100 5 channels 0 0000 0101 ... ... 509 channels 1 1111 1101 510 channels 1 1111 1110 511 channels 1 1111 1111 table 23 - local input channel delay (lcd) programming table
zl50060/1 data sheet 64 zarlink semiconductor inc. 14.5 local input bit delay registers (lidr0 to lidr31) addresses 0023 h to 0042 h . there are thirty-two local input delay registers (lidr0 to lidr31). when the smpl_mode bit in the control register is low, the input data sampling point defaults to the 3/4 bit location and lidr0 to lidr31 define the input bit and fractional bit delay of each local stream. the possible bit delay adjustment is up to 7 3 / 4 bits, in steps of 1 / 4 bit. when the smpl_mode bit is high, lidr0 to lidr31 define the input bit sampling point as well as the integer bit delay of each local stream. the input bit sampling point can be adjusted in 1/4 bit increments. the bit delay can be adjusted in 1-bit increments from 0 to 7 bits. the lidr0 to lidr31 registers are configured as follows: table 24 - local input bit delay register (lidrn) bits 14.5.1 local input delay bits 4-0 (lid[4:0]) when smpl_mode = low, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. input bit delay adjustment can range up to 7 3 / 4 bit periods forward, with resolution of 1 / 4 bit period. the default sampling point is at the 3 / 4 bit location. this can be described as: no. of bits delay = lid[4:0] / 4 for example, if lid[4:0] is set to 10011 (19), the input bit delay = 19 * 1 / 4 = 4 3 / 4 . when smpl_mode = high, the binary value of lid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). lid[4:2] refer to the integer bit delay value (0 to 7 bits). this means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1 / 4 to 4 / 4 in 1 / 4 -bit increments. table 25 illustrates the bit delay and sampling point selection. lidrn bit (where n = 0 to 31 for local non-32mbps mode, n = 0 to 15 for local 32mbps mode) name reset value description 15:5 reserved 0 reserved must be set to 0 for normal operation 4:0 lid[4:0] 0 local input bit delay register when smpl_mode = low, the binary value of these bits refers to the input bit and fractional bit delay value (0 to 7 3 / 4 ). when smpl_mode = high, the binary value of lid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). lid[4:2] refer to the integer bit delay value (0 to 7 bits). lidn smpl_mode = low smpl_mode = high lid4 lid3 lid2 lid1 lid0 input data bit delay input data bit delay input data sampling point 000000 (default)0 (default) 3/4 00001 1/4 0 4/4 table 25 - local input bit delay and sampling point programming table
zl50060/1 data sheet 65 zarlink semiconductor inc. 00010 1/2 0 1/4 00011 3/4 0 2/4 00100 1 1 3/4 00101 1 1/4 1 4/4 00110 1 1/2 1 1/4 00111 1 3/4 1 2/4 01000 2 2 3/4 01001 2 1/4 2 4/4 01010 2 1/2 2 1/4 01011 2 3/4 2 2/4 01100 3 3 3/4 01101 3 1/4 3 4/4 01110 3 1/2 3 1/4 01111 3 3/4 3 2/4 10000 4 4 3/4 10001 4 1/4 4 4/4 10010 4 1/2 4 1/4 10011 4 3/4 4 2/4 10100 5 5 3/4 10101 5 1/4 5 4/4 10110 5 1/2 5 1/4 10111 5 3/4 5 2/4 11000 6 6 3/4 11001 6 1/4 6 4/4 11010 6 1/2 6 1/4 11011 6 3/4 6 2/4 11100 7 7 3/4 11101 7 1/4 7 4/4 11110 7 1/2 7 1/4 11111 7 3/4 7 2/4 lidn smpl_mode = low smpl_mode = high lid4 lid3 lid2 lid1 lid0 input data bit delay input data bit delay input data sampling point table 25 - local input bit delay and sampling point programming table (continued)
zl50060/1 data sheet 66 zarlink semiconductor inc. 14.6 backplane input channel delay registers (bcdr0 to bcdr31) addresses 0043 h to 0062 h thirty-two backplane input channel delay registers (bcdr0 to bcdr31) allow users to program the input channel delay for the backplane input data streams bsti0-31. the maximum possible adjustment is 511 channels and the bcdr0 to bcdr31 registers are configured as follows: 14.6.1 backplane channel delay bits 8-0 (bcd8 - bcd0) these nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the backplane input pins. the input channel delay can be selected to be up to 511 (32mbps streams), 255 (16mbps streams), 127 (8mbps streams), 63 (4mbps streams) or 31 (2mbps streams) channels from the frame boundary. bcdrn bit (where n = 0 to 31 for backplane non-32mbps mode, n = 0 to 15 for backplane 32mbps mode) name reset value description 15:9 reserved 0 reserved must be set to 0 for normal operation 8:0 bcd[8:0] 0 backplane channel delay register the binary value of these bits refers to the channel delay value for the backplane input stream. table 26 - backplane input channel delay register (bcdrn) bits input stream channel delay corresponding delay bits bcd8-bcd0 0 channel (default) 0 0000 0000 1 channel 0 0000 0001 2 channels 0 0000 0010 3 channels 0 0000 0011 4 channels 0 0000 0100 5 channels 0 0000 0101 ... ... 509 channels 1 1111 1101 510 channels 1 1111 1110 511 channels 1 1111 1111 table 27 - backplane input channel delay (bcd) programming table
zl50060/1 data sheet 67 zarlink semiconductor inc. 14.7 backplane input bit delay registers (bidr0 to bidr31) addresses 0063 h to 0082 h there are thirty-two backplane input delay registers (bidr0 to bidr31). when the smpl_mode bit in the control register is low, the input data sampling point defaults to the 3/4 bit location and bidr0 to bidr31 define the input bit and fractional bit delay of each backplane stream. the possible bit delay adjustment is up to 7 3 / 4 bits, in steps of 1 / 4 bit. when the smpl_mode bit is high, bidr0 to bidr31 define the input bit sampling point as well as the integer bit delay of each backplane stream. the input bit sampling point can be adjusted in 1/4 bit increments. the bit delay can be adjusted in 1-bit increments from 0 to 7 bits. the bidr0 to bidr31 registers are configured as follows: table 28 - backplane input bit delay register (bidrn) bits bidrn bit (where n = 0 to 31 for backplane non-32mbps mode, n = 0 to 15 for backplane 32mbps mode) name reset value description 15:5 reserved 0 reserved must be set to 0 for normal operation 4:0 bid[4:0] 0 backplane input bit delay register when smpl_mode = low, the binary value of these bits refers to the input bit and fractional bit delay value (0 to 7 3 / 4 ). when smpl_mode = high, the binary value of bid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). bid[4:2] refer to the integer bit delay value (0 to 7 bits).
zl50060/1 data sheet 68 zarlink semiconductor inc. 14.7.1 backplane input delay bits 4-0 (bid[4:0]) when smpl_mode = low, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. input bit delay adjustment can range up to 7 3 / 4 bit periods forward, with resolution of 1 / 4 bit period. the default sampling point is at the 3 / 4 bit location. this can be described as: no. of bits delay = bid[4:0] / 4 for example, if bid[4:0] is set to 10011 (19), the input bit delay = 19 * 1 / 4 = 4 3 / 4. when smpl_mode = high, the binary value of bid[1:0] refers to the input bit sampling point ( 1 / 4 to 4 / 4 ). bid[4:2] refer to the integer bit delay value (0 to 7 bits). this means that bits can be delayed by an integer value of up to 7 and that the sampling point can vary from 1 / 4 to 4 / 4 in 1 / 4 -bit increments. table 29 illustrates the bit delay and sampling point selection. bidn smpl_mode = low smpl_mode = high bid4 bid3 bid2 bid1 bid0 input data bit delay input data bit delay input data sampling point 000000 (default)0 (default) 3/4 00001 1/4 0 4/4 00010 1/2 0 1/4 00011 3/4 0 2/4 00100 1 1 3/4 00101 1 1/4 1 4/4 00110 1 1/2 1 1/4 00111 1 3/4 1 2/4 01000 2 2 3/4 01001 2 1/4 2 4/4 01010 2 1/2 2 1/4 01011 2 3/4 2 2/4 01100 3 3 3/4 01101 3 1/4 3 4/4 01110 3 1/2 3 1/4 01111 3 3/4 3 2/4 10000 4 4 3/4 10001 4 1/4 4 4/4 10010 4 1/2 4 1/4 10011 4 3/4 4 2/4 10100 5 5 3/4 10101 5 1/4 5 4/4 10110 5 1/2 5 1/4 10111 5 3/4 5 2/4 11000 6 6 3/4 11001 6 1/4 6 4/4 11010 6 1/2 6 1/4 11011 6 3/4 6 2/4 table 29 - backplane input bit delay and sampling point programming table
zl50060/1 data sheet 69 zarlink semiconductor inc. 14.8 local output advancement registers (loar0 to loar31) addresses 0083 h to 00a2 h . thirty-two local output advancement registers (loar0 to loar31) allow users to program the output advancement for output data streams lsto0 to lsto31. for 2mbps, 4mbps, 8mbps and 16mbps stream operation, the possible adjustment is -2 (15ns), -4 (31ns) or -6 (46ns) cycles of the internal system clock (131.072mhz). for 32mbps stream operation, the possible adjustment is -1 (7.6ns), -2 (15ns) or -3 (23ns) cycles of the internal system clock (131.072mhz). the loar0 to loar31 registers are configured as follows: table 30 - local output advancement register (loar) bits 14.8.1 local output advancement bits 1-0 (loa1-loa0) the binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. when the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse fp8o . 11100 7 7 3/4 11101 7 1/4 7 4/4 11110 7 1/2 7 1/4 11111 7 3/4 7 2/4 loarn bit (where n = 0 to 31 for local non-32mbps mode, n = 0 to 15 for local 32mbps mode) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 loa[1:0] 0 local output advancement value local output advancement for 2mbps, 4mbps, 8mbps & 16mbps local output advancement for 32mbps corresponding advancement bits clock rate 131.072 mhz clock rate 131.072 mhz loa1 loa0 0 (default) 0 (default) 0 0 -2 cycles (~15ns) -1 cycle (~7.6ns) 0 1 table 31 - local output advancement (loar) programming table bidn smpl_mode = low smpl_mode = high bid4 bid3 bid2 bid1 bid0 input data bit delay input data bit delay input data sampling point table 29 - backplane input bit delay and sampling point programming table (continued)
zl50060/1 data sheet 70 zarlink semiconductor inc. 14.9 backplane output advancement registers (boar0 - boar31) addresses 00a3 h to 00c2 h thirty-two backplane output advancement registers (boar0 to boar31) allow users to program the output advancement for output data streams bsto0 to bsto31. for 2mbps, 4mbps, 8mbps and 16mbps stream operation, the possible adjustment is -2 (15ns), -4 (31ns) or -6 (46ns) cycles of the internal system clock (131.072mhz). for 32mbps stream operation, the possible adjustment is -1 (7.6ns), -2 (15ns) or -3 (23ns) cycles of the internal system clock (131.072mhz). the boar0 to boar31 registers are configured as follows: table 32 - backplane output advancement register (boar) bits 14.9.1 backplane output advancement bits 1-0 (boa1-boa0) the binary value of these two bits indicates the amount of offset that a particular stream output can be advanced with respect to the output frame boundary. when the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse fp8o . -4 cycles (~31ns) -2 cycles (~15ns) 1 0 -6 cycles (~46ns) -3 cycles (~23ns) 1 1 boarn bit (where n = 0 to 31 for backplane non-32mbps mode, n = 0 to 15 for backplane 32mbps mode) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 boa[1:0] 0 backplane output advancement value backplane output advancement for 2mbps, 4mbps, 8mbps & 16mbps backplane output advancement for 32mbps corresponding advancement bits clock rate 131.072 mhz clock rate 131.072 mhz boa1 boa0 0 (default) 0 (default) 0 0 -2 cycles (~15ns) -1 cycle (~7.6ns) 0 1 -4 cycles (~31ns) -2 cycles (~15ns) 1 0 -6 cycles (~46ns) -3 cycles (~23ns) 1 1 table 33 - backplane output advancement (boar) programming table local output advancement for 2mbps, 4mbps, 8mbps & 16mbps local output advancement for 32mbps corresponding advancement bits clock rate 131.072 mhz clock rate 131.072 mhz loa1 loa0 table 31 - local output advancement (loar) programming table (continued)
zl50060/1 data sheet 71 zarlink semiconductor inc. 14.10 local bit error rate (ber) registers 14.10.1 local ber start send register (lbssr) address 00c3 h . the local ber start send register defines the output channel and the stream on which the ber sequence starts to be transmitted. the lbssr register is configured differently for non-32mbps and 32mbps modes: table 34 - local ber start send register (lbssr) bits in non-32mbps mode table 35 - local ber start send register (lbssr) bits in 32mbps mode bit name reset value description 15:13 reserved 0 reserved must be set to 0 for normal operation 12:8 lbssa[4:0] 0 local ber send stream address bits the binary value of these bits refers to the local output stream which carries the ber data. 7:0 lbsca[7:0] 0 local ber send channel address bits the binary value of these bits refers to the local output channel at which the ber data starts to be sent. bit name reset value description 15:13 reserved 0 reserved must be set to 0 for normal operation 12:9 lbssa[3:0] 0 local ber send stream address bits the binary value of these bits refers to the local output stream which carries the ber data. 8:0 lbsca[8:0] 0 local ber send channel address bits the binary value of these bits refers to the local output channel at which the ber data starts to be sent.
zl50060/1 data sheet 72 zarlink semiconductor inc. 14.10.2 local transmit ber length register (ltxblr) address 00c4 h . local ber transmit length register ( ltxblr ) defines how many channels of the ber sequence will be transmitted during each frame. the minimum length of the ber transmitter is 1 channel. to set a desired ber length, set ltxbl8-0 bits for the desired length - 1 channel. for example, to run a ber test for 32 consecutive channels, program ltxbl to 000011111 b . the ltxblr register is configured as follows: table 36 - local ber length register (ltxblr) bits 14.10.3 local receive ber length register (lrxblr) address 00c5 h . local ber receive length register ( lrxblr ) defines how many channels of the ber sequence will be received during each frame. the minimum length of the ber receiver is 1 channel. to set a desired ber length, set lrxbl8-0 bits for the desired length - 1 channel. for example, to receive a ber test for 32 consecutive channels, program lrxbl to 000011111 b . the lrxblr register is configured as follows: table 37 - local receive ber length register (lrxblr) bits bit name reset value description 15:9 reserved 0 reserved must be set to 0 for normal operation 8:0 ltxbl[8:0] 0 local transmit ber length bits the binary value of these bits defines the number of channels in addition to the start channel allocated for the ber transmitter. (i.e. total channels = ltxbl value + 1) bit name reset value description 15:9 reserved 0 reserved must be set to 0 for normal operation 8:0 lrxbl[8:0] 0 local receive ber length bits the binary value of these bits defines the number of channels in addition to the start channel allocated for the ber receiver. (i.e. total channels = lrxbl value + 1)
zl50060/1 data sheet 73 zarlink semiconductor inc. 14.10.4 local ber start receive register (lbsrr) address 00c6 h . local ber start receive register defines the input stream and start channel at which the ber sequence shall start to be received. the lbsrr register is configured differently for non-32mbps and 32mbps modes: 14.10.5 local ber count register (lbcr) address 00c7 h . local ber count register contains the number of counted errors. this register is read-only. the lbcr register is configured as follows: table 40 - local ber count register (lbcr) bits bit name reset value description 15:13 reserved 0 reserved must be set to 0 for normal operation 12:8 lbrsa[4:0] 0 local ber receive stream address bits the binary value of these bits refers to the local input stream configured to receive the ber data. 7:0 lbrca[7:0] 0 local ber receive channel address bits the binary value of these bits refers to the local input channel at which the ber data starts to be compared. table 38 - local ber start receive register (lbsrr) bits for non-32mbps mode bit name reset value description 15:13 reserved 0 reserved must be set to 0 for normal operation 12:9 lbrsa[3:0] 0 local ber receive stream address bits the binary value of these bits refers to the local input stream configured to receive the ber data. 8:0 lbrca[8:0] 0 local ber receive channel address bits the binary value of these bits refers to the local input channel at which the ber data starts to be compared. table 39 - local ber start receive register (lbsrr) bits for 32mbps mode bit name reset value description 15:0 lbc[15:0] 0 local bit error rate count the binary value of the bits defines the local bit error count. if the number of errors exceeds the maximum counter value, this counter will stay at ffff h until the cberl bit in the bercr register clears it.
zl50060/1 data sheet 74 zarlink semiconductor inc. 14.11 backplane bit error rate (ber) registers 14.11.1 backplane ber start send register (bbssr) address 00c8 h . backplane ber start send register defines the output channel and the stream on which the ber sequence is transmitted. the bbssr register is configured as follows: table 41 - backplane ber start send register (bbssr) bits 14.11.2 backplane transmit ber length register (btxblr) address 00c9 h . backplane transmit ber length register ( btxblr ) defines how many channels of the ber sequence will be transmitted in each frame. the minimum length of the ber transmitter is 1 channel. to set a desired ber length, set btxbl8-0 bits for the desired length - 1 channel. for example, to run a ber test for 32 consecutive channels, program btxbl to 000011111 b . the btxblr register is configured as follows: table 42 - backplane transmit ber length (btxblr) bits bit name reset value description 15:14 reserved 0 reserved must be set to 0 for normal operation 13:9 bbssa[4:0] 0 backplane ber send stream address bits the binary value of these bits refers to the backplane output stream which carries the ber data. 8:0 bbsca[8:0] 0 backplane ber send channel address bits the binary value of these bits refers to the backplane output channel at which the ber data starts to be sent. bit name reset value description 15:9 reserved 0 reserved must be set to 0 for normal operation 8:0 btxbl[8:0] 0 backplane transmit ber length bits the binary value of these bits defines the number of channels in addition to the start channel allocated for the ber transmitter. (i.e. total channels = btxbl value + 1)
zl50060/1 data sheet 75 zarlink semiconductor inc. 14.11.3 backplane receive ber length register (brxblr) address 00ca h . backplane receive ber length register ( brxblr ) defines how many channels of the ber sequence will be received in each frame. the minimum length of the ber receiver is 1 channel. to set a desired ber length, set brxbl8-0 bits for the desired length - 1 channel. for example, to receive a ber test for 32 consecutive channels, program brxbl to 000011111 b . the brxblr register is configured as follows: table 43 - backplane receive ber length (brxblr) bits 14.11.4 backplane ber start receive register (bbsrr) address 00cb h . backplane ber start receive register defines the input stream and the start channel at which the ber sequence shall start to be received. the bbsrr register is configured as follows: table 44 - backplane ber start receive register (bbsrr) bits bit name reset value description 15:9 reserved 0 reserved must be set to 0 for normal operation 8:0 brxbl[8:0] 0 backplane receive ber length bits the binary value of these bits defines the number of channels in addition to the start channel allocated for the ber receiver. (i.e. total channels = brxbl value + 1) bit name reset value description 15:14 reserved 0 reserved must be set to 0 for normal operation 13:9 bbrsa[4:0] 0 backplane ber receive stream address bits the binary value of these bits refers to the backplane input stream configured to receive the ber data. 8:0 bbrca[8:0] 0 backplane ber receive channel address bits the binary value of these bits refers to the backplane input channel at which the ber data starts to be compared.
zl50060/1 data sheet 76 zarlink semiconductor inc. 14.11.5 backplane ber count register (bbcr) address 00cc h . backplane ber count register contains the number of counted errors. this register is read-only. the bbcr register is configured as follows: table 45 - backplane ber count register (bbcr) bits 14.12 local bit rate registers 14.12.1 local input bit rate registers (librr0 - librr31) addresses 00cd h to 00ec h . thirty-two local input bit rate registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16mbps. these registers may be overridden by setting local 32mbps mode in the control register (via the mode32l bit), in which case, local input streams 0-15 will operate at 32mbps and local input streams 16-31 will be unused. the librr registers are configured as follows: table 46 - local input bit rate register (librr) bits table 47 - local input bit rate (libr) programming table bit name reset value description 15:0 bbc[15:0] 0 backplane bit error rate count the binary value of these bits defines the backplane bit error count. if the number of errors exceeds the maximum counter value, this counter will stay at ffff h until the cberb bit in the bercr register clears it. librn (for n=0 to 31) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 libr[1:0] 0 local input bit rate mode32l libr1 libr0 bit rate for stream n 000 2mbps 001 4mbps 010 8mbps 0 1 1 16mbps 1 x x 32mbps
zl50060/1 data sheet 77 zarlink semiconductor inc. 14.12.2 local output bit rate registers (lobrr0 - lobrr31) addresses 00ed h to 010c h . thirty-two local output bit rate registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16mbps. these registers may be overridden by setting local 32mbps mode in the control register (via the mode32l bit), in which case, local output streams 0-15 will operate at 32mbps and local output streams 16-31 will be unused. the lobrr registers are configured as follows: table 48 - local output bit rate register (lobrr) bits table 49 - local output bit rate (lobr) programming table 14.13 backplane bit rate registers 14.13.1 backplane input bit rate registers (bibrr0 - bibrr31) addresses 010d h to 012c h . thirty-two backplane input bit rate registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 mbps. these registers may be overridden by setting backplane 32mbps mode in the control register (via the mode32b bit), in which case, backplane input streams 0-15 will operate at 32mbps and backplane input streams 16-31 will be unused. the bibrr registers are configured as follows: table 50 - backplane input bit rate register (bibrr) bits lobrn bit (where n = 0 to 31) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 lobr[1:0] 0 local output bit rate mode32l lobr1 lobr0 bit rate for stream n 0 0 0 2mbps 0 0 1 4mbps 0 1 0 8mbps 011 16mbps 1xx 32mbps bibrn bit (for n = 0 to 31) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 bibr[1:0] 0 backplane input bit rate
zl50060/1 data sheet 78 zarlink semiconductor inc. table 51 - backplane input bit rate (bibr) programming table 14.13.2 backplane output bit rate registers (bobrr0 - bobrr31) addresses 012d h to 014c h . thirty-two backplane output bit rate registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 mbps. these registers may be overridden by setting backplane 32mbps mode in the control register (via the mode32b bit), in which case, backplane output streams 0-15 will operate at 32mbps and backplane output streams 16-31 will be unused. the bobrr registers are configured as follows: table 52 - backplane output bit rate register (bobrr) bits table 53 - backplane output bit rate (bobrr) programming table mode32b bibr1 bibr0 bit rate for stream n 000 2mbps 001 4mbps 010 8mbps 0 1 1 16mbps 1 x x 32mbps bobrn bit (for n = 0 to 31) name reset value description 15:2 reserved 0 reserved must be set to 0 for normal operation 1:0 bobr[1:0] 0 backplane output bit rate mode32b bobr1 bobr0 bit rate for stream n 000 2mbps 001 4mbps 010 8mbps 0 1 1 16mbps 1 x x 32mbps
zl50060/1 data sheet 79 zarlink semiconductor inc. 14.14 memory bist register address 014d h . the memory bist register enables the self-test of chip memory. two consecutive write operations are required to start mbist: the first with only bit 12 (lv_tm) set high (i.e. 1000h); the second with bit 12 maintained high but with the required start bit(s) also set high. the mbistr register is configured as follows: bit name reset value description 15:13 reserved 0 reserved must be set to 0 for normal operation 12 lv_tm 0 mbist test enable set high to enable mbist mode. set low for normal operation. 11 bistsdb 0 backplane data memory start bist sequence sequence enabled on low to high transition. 10 bistcdb 0 backplane data memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of backplane data memory bist sequence. 9bistpdb 0 backplane data memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the backplane data memory bist sequence (indicated by assertion of bistcdb). a high indicates pass, a low indicates fail. 8bistsdl 0 local data memory start bist sequence sequence enabled on low to high transition. 7 bistcdl 0 local data memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of local data memory bist sequence. 6bistpdl 0 local data memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the local data memory bist sequence (indicated by assertion of bistcdl). a high indicates pass, a low indicates fail. 5bistscb 0 backplane connection memory start bist sequence sequence enabled on low to high transition. 4bistccb 0 backplane connection memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of backplane connection memory bist sequence. 3bistpcb 0 backplane connection memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the backplane connection memory bist sequence (indicated by assertion of bistccb). a high indicates pass, a low indicates fail. 2bistscl 0 local connection memory start bist sequence sequence enabled on low to high transition. table 54 - memory bist register (mbistr) bits
zl50060/1 data sheet 80 zarlink semiconductor inc. 14.15 device identification register address 3fff h . the device identification register stores the binary value of the silicon revision number and the device id. this register is read-only. the dir register is configured as follows: table 55 - device identification register (dir) bits 1 bistccl 0 local connection memory bist sequence completed (read-only) this bit must be polled - when high, indicates completion of local connection memory bist sequence. 0bistpcl 0 local connection memory pass/fail bit (read-only) this bit indicates the pass/fail status following completion of the local connection memory bist sequence (indicated by assertion of bistccl). a high indicates pass, a low indicates fail. bit name reset value description 15:8 reserved 0 reserved will read 0 in normal operation 7:4 rc[3:0] 0000 revision control bits 3 reserved 0 reserved will read 0 in normal operation 2:0 did[2:0] 000 device id bit name reset value description table 54 - memory bist register (mbistr) bits (continued)
zl50060/1 data sheet 81 zarlink semiconductor inc. 15.0 dc electrical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. voltages are with respect to ground (v ss ) unless otherwise stated. absolute maximum ratings* parameter symbol min max units 1 core supply voltage v dd_core -0.5 2.5 v 2 i/o supply voltage v dd_io -0.5 5.0 v 3 pll supply voltage v dd_pll -0.5 2.5 v 4 input voltage (non-5v tolerant inputs) v i -0.5 v dd_io +0.5 v 5 input voltage (5v tolerant inputs) v i_5v -0.5 7.0 v 6 continuous current at digital outputs i o 15 ma 7 package power dissipation p d 1.5 w 8 storage temperature t s - 55 +125 c recommended operating conditions characteristics sym min typ max units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_io 3.0 3.3 3.6 v 3 positive supply v dd_core 1.71 1.8 1.89 v 4 positive supply v dd_pll 1.71 1.8 1.89 v 5 input voltage v i 0v dd_io v 6 input voltage on 5v tolerant inputs v i_5v 05.5v
zl50060/1 data sheet 82 zarlink semiconductor inc. voltages are with respect to ground (v ss ) unless otherwise stated. note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage (v) dc electrical parameters characteristics sym min typ max units test conditions 1a i n p u t s supply current i dd_core 4mastatic idd_core and pll current 1b supply current i dd_core 240 290 ma applied clock c8i = 8.192 mhz 1c supply current i dd_io 100 astatic i dd_io 1d supply current i dd_io 14 18 ma i av with all output streams at max. data rate unloaded 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage (input pins) input leakage (bi-directional pins) i il i bl 5 5 a a 0 < v < v dd_io note 1 weak pullup current i pu 200 a input at 0v 5 weak pulldown current i pd 200 a input at v dd_io 6 input pin capacitance c i 5pf 7o u t p u t s output high voltage v oh 2.4 v i oh = 8ma 8 output low voltage v ol 0.4 v i ol = 8ma 9 high impedance leakage i oz 5 a0 < v 0 < v dd_io note 1 10 output pin capacitance c o 5pf
zl50060/1 data sheet 83 zarlink semiconductor inc. 16.0 ac electrical characteristics ac electrical characteristics timing parameter measurement: voltage levels characteristics sym level units conditions 1 cmos threshold v ct 0.5v dd_io v3.0v < v dd_io < 3.6v 2 rise/fall threshold voltage high v hm 0.7v dd_io v3.0v < v dd_io < 3.6v 3 rise/fall threshold voltage low v lm 0.3v dd_io v3.0v < v dd_io < 3.6v input and output clock timing characteristic sym min typ max units notes 1fp8i , input frame pulse width t ifpw244 t ifpw122 210 10 244 122 350 220 ns 2 input frame pulse setup time (before c8i clock falling/rising edge) t ifps244 t ifps122 5 5 110 60 ns 3 input frame pulse hold time (from c8i clock falling/rising edge) t ifph244 t ifph122 0 0 110 60 ns 4c8i clock period (average value, does not consider the effects of jitter) t icp 120 122 124 ns 5c8i clock pulse width high t ich 50 61 70 ns 6c8i clock pulse width low t icl 50 61 70 ns 7c8i clock rise/fall time t ric , t fic 02 3 ns 8c8i cycle to cycle variation (this values is with respect to the typical c8i clock period, and using mid-bit sampling) t ccvic -7.0 -8.5 7.0 8.5 ns ns 32mbps 16mbps or lower. 9 output frame boundary offset t ofbos 79.5ns 10 fp8o frame pulse width t ofpw8_244 t ofpw8_122 224 117 244 122 264 127 ns fpw =1 fpw=0 c l =60pf 11 fp8o output delay (from frame pulse edge to output frame boundary) t fpfbf8_244 t fpfbf8_122 117 58 122 61 127 64 ns fpw =1 fpw=0 c l =60pf 12 fp8o output delay (from output frame boundary to frame pulse edge) t fbfpf8_244 t fbfpf8_122 117 58 122 61 127 64 ns fpw =1 fpw=0 c l =60pf 13 c8o clock period t ocp8 117 122 127 ns c l =60pf 14 c8o clock pulse width high t och8 58 61 64 ns 15 c8o clock pulse width low t ocl8 58 61 64 ns 16 c8o clock rise/fall time t roc8 , t foc8 37ns
zl50060/1 data sheet 84 zarlink semiconductor inc. 17 fp16o frame pulse width t ofpw16_122 t ofpw16_61 117 58 122 61 127 64 ns fpw =1 fpw=0 c l =60pf 18 fp16o output delay (from frame pulse edge to output frame boundary) t fpfbf16_122 t fpfbf16_61 58 29 61 31 64 33 ns fpw =1 fpw=0 19 fp16o output delay (from output frame boundary to frame pulse edge) t fbfpf16_122 t fbfpf16_61 58 29 61 31 64 33 ns fpw =1 fpw=0 20 c16o clock period t ocp16 58 61 64 ns c l =60pf 21 c16o clock pulse width high t och16 29 31 33 ns 22 c16o clock pulse width low t ocl16 29 31 33 ns 23 c16o clock rise/fall time t roc16 , t foc16 37ns input and output clock timing (continued) characteristic sym min typ max units notes
zl50060/1 data sheet 85 zarlink semiconductor inc. figure 25 - input and output clock timing diagram for st-bus t ifpw122 t ifph122 t ifps122 ck_int * t fbfpf8_122 t fpfbf8_122 t fpfb16_61 t och8 t ocl8 t ocl16 t och16 t ocp8 t ocp16 t foc8 t roc8 t roc16 t foc16 t ofbos note *: ck_int is the internal clock signal of 131.072mhz fp8o c8o fp16o c16o fp8i c8i t ich t icl t icp t fic t ric t fbfpf8_244 t fpfbf8_244 t ifpw244 t ifph244 t ifps244 fp8i fp8o (244ns) (122ns) (244ns) (122ns) t ofpw8_122 t ofpw16_61 t fbfpf16_122 t fpfbf16_122 fp 16o (122ns) t ofpw8_244 t ofpw16_122 (61ns) t fbfp16_61 note **: although the figures above show the frame boundary as measured from the falling edge of c8i /c8o /c16o , the frame-controlling edge of c8i /c8o /c16o may be the rising edge, as configured via the c8ipol and copol bits of the control register.
zl50060/1 data sheet 86 zarlink semiconductor inc. figure 26 - input and output clock timing diagram for gci-bus t ifpw122 t ifph122 t ifps122 ck_int * t fbfpf8_122 t fpfbf8_122 t fpfb16_61 t och8 t ocl8 t ocl16 t och16 t ocp8 t ocp16 t foc8 t roc8 t roc16 t foc16 t ofbos note *: ck_int is the internal clock signal of 131.072mhz fp8o c8o fp16o c16o fp8i c8i t ich t icl t fic t ric t fbfpf8_244 t fpfbf8_244 t ifph244 t ifps244 fp8i fp8o (244ns) (122ns) (244ns) (122ns) t ofpw8_122 t ofpw16_61 t fbfpf16_122 t fpfbf16_122 fp 16o (122ns) t ofpw8_244 t ofpw16_122 (61ns) t fbfp16_61 note **: although the figures above show the frame boundary as measured from the rising edge of c8i /c8o /c16o , the frame-controlling edge of c8i /c8o /c16o may be the rising edge, as configured via the c8ipol and copol bits of the control register. t ifpw244 t icp
zl50060/1 data sheet 87 zarlink semiconductor inc. local and backplane data timing characteristic sym min typ max units notes 1 local/backplane input data sampling point t ids32 t ids16 t ids8 t ids4 t ids2 20 43 87 178 357 23 46 92 183 366 26 49 97 188 375 ns with smpl_mode = 0 (3/4-bit sampling) and zero offset. 2 local/backplane serial input set-up time t sis32 t sis16 t sis8 t sis4 t sis2 2 2 2 2 2 ns with respect to min . input data sampling point 3 local/backplane serial input hold time t sih32 t sih16 t sih8 t sih4 t sih2 2 2 2 2 2 ns with respect to max . input data sampling point 4 output frame boundary offset t ofbos 79.5ns 5 local/backplane serial output delay t sod32 t sod16 t sod8 t sod4 t sod2 4.5 4.5 4.5 4.5 4.5 ns c l =50pf these numbers are referencing output frame boundary.
zl50060/1 data sheet 88 zarlink semiconductor inc. figure 27 - st-bus local/backplane data timing diagram (8mbps, 4mbps, 2mbps) ck_int * l/bsti0-31 l/bsto0-31 t ids8 8.192mbps 8.192mbps note *: ck_int is the internal clock signal of 131.072mhz fp8i c8i t ids4 t ids2 t sih8 t sis8 t sih4 t sis4 t sih2 t sis2 t sod2 t sod4 t sod8 l/bsto0-31 4.096mbps l/bsto0-31 2.048mbps l/bsti0-31 4.096mbps l/bsti0-31 2.048mbps bit7 ch0 bit6 ch0 bit7 ch0 bit6 ch0 bit0 ch31 bit0 ch63 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit7 ch0 bit6 ch0 bit0 ch31 bit5 ch0 bit4 ch0 bit6 ch0 bit7 ch0 bit0 ch63 bit1 ch127 bit0 ch127 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 6 5 0 4 3 2 1 1 7 fp8o c8o t ofbos ck_int *
zl50060/1 data sheet 89 zarlink semiconductor inc. figure 28 - st-bus local/backplane data timing diagram (32mbps, 16mbps) ck_int * fp8o c8 o l/bsti0-15 l/bsto0-15 t ids32 32.768mbps 32.768mbps t ids16 t sih32 t sis32 t sih16 t sis16 t sod16 t sod32 l/bsto0-31 16.384mbps l/bsti0-31 16.384mbps bit0 ch255 bit7 ch0 bit6 ch0 bit5 ch0 bit7 ch0 bit6 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch255 bit1 ch511 bit0 ch511 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 6 5 0 4 3 2 1 7 note *: ck_int is the internal clock signal of 131.072mhz 2 bit1 ch511 bit1 ch255 ck_int * fp8i c8i t ofbos
zl50060/1 data sheet 90 zarlink semiconductor inc. figure 29 - gci-bus local/backplane data timing diagram (8mbps, 4mbps, 2mbps) ck_int * l/bsti0-31 l/bsto0-31 t ids8 8.192mbps 8.192mbps note *: ck_int is the internal clock signal of 131.072mhz fp8i c8i t ids4 t ids2 t sih8 t sis8 t sih4 t sis4 t sih2 t sis2 t sod2 t sod4 t sod8 l/bsto0-31 4.096mbps l/bsto0-31 2.048mbps l/bsti0-31 4.096mbps l/bsti0-31 2.048mbps bit0 ch0 bit1 ch0 bit0 ch0 bit1 ch0 bit7 ch31 bit7 ch63 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit0 ch0 bit1 ch0 bit7 ch31 bit2 ch0 bit3 ch0 bit1 ch0 bit0 ch0 bit7 ch63 bit6 ch127 bit7 ch127 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 1 2 7 3 4 5 6 6 0 ck_int * fp8o c8o t ofbos
zl50060/1 data sheet 91 zarlink semiconductor inc. figure 30 - gci-bus local/backplane data timing diagram (32mbps, 16mbps) ck_int * fp8i c8i l/bsti0-15 l/bsto0-15 t ids32 32.768mbps 32.768mbps t ids16 t sih32 t sis32 t sih16 t sis16 t sod16 t sod32 l/bsto0-31 16.384mbps l/bsti0-31 16.384mbps bit7 ch255 bit0 ch0 bit1 ch0 bit2 ch0 bit0 ch0 bit1 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit6 ch511 bit7 ch511 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 6 5 0 4 3 2 1 7 note *: ck_int is the internal clock signal of 131.072mhz 2 bit5 ch511 bit6 ch255 bit7 ch255 ck_int * fp8o c8 o t ofbos
zl50060/1 data sheet 92 zarlink semiconductor inc. note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 31 - serial output and external control figure 32 - output driver enable (ode) local and backplane output high impedance timing characteristic sym min typ max units test conditions 1 sto delay - active to high-z - high-z to active t dz t zd 4 4 6 6 ns ns r l =1k, c l =50pf, see note 1 2 output driver enable (ode) delay to active data output driver enable (ode) delay to high impedance t ode t odz 14 14 ns ns r l =1k, c l =50pf, see note 1 r l =1k, c l =50pf, see note 1 t dz sto t zd sto clk vtt vtt hiz valid data vtt hiz valid data vtt hi-z hi-z sto ode t odz t ode valid data vtt
zl50060/1 data sheet 93 zarlink semiconductor inc. input clock jitter tolerance jitter frequency 16.384mbps data rate jitter tolerance 32.768mbps data rate jitter tolerance units 1 1khz 1200 600 ns 2 10khz 1200 600 ns 3 50khz 150 80 ns 4 66khz 110 50 ns 5 83khz 80 35 ns 6 95khz 70 30 ns 7 100khz 25 20 ns 8 200khz 17 14 ns 9 300khz 17 14 ns 10 400khz 17 14 ns 11 500khz 17 14 ns 12 1mhz 17 14 ns 13 2mhz 17 14 ns 14 4mhz 17 14 ns
zl50060/1 data sheet 94 zarlink semiconductor inc. note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: there must be a minimum of 30ns between cpu accesses, to allow the device to recognize the accesses as separate (i.e., a minimum of 30ns must separate the de-assertion of dta (to high) and the assertion of cs and/or ds to initiate the next access). non-multiplexed microprocessor port timing characteristics sym min typ max units test conditions 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 9ns 3 address setup from ds falling t ads 9ns 4cs hold after ds rising t csh 0ns 5r/w hold after ds rising t rwh 9ns 6 address hold after ds rising t adh 9ns 7 data setup from dta low on read t rds 5 12 ns ns memory read register read c l =60pf 8 data hold on read t rdh 4.5 ns c l =60pf, r l =1k note 1 9 data setup on write t wds 9ns 10 data hold on write t wdh 9ns 11 acknowledgment delay: reading/writing registers reading/writing memory t akd 88 80 ns ns c l =60pf c l =60pf 12 acknowledgment hold time t akh 11 ns c l =60pf, r l =1k, note 1
zl50060/1 data sheet 95 zarlink semiconductor inc. figure 33 - motorola non-multiplexed bus timing a0-a14 d0-d15 d0-d15 read write t css t csh t adh t rdh t rws t ads t rwh t wdh t akd t rds t akh v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data dta r/w cs ds t wds
zl50060/1 data sheet 96 zarlink semiconductor inc. ?characteristics are over recommended operating conditions unless otherwise stated. figure 34 - jtag test port timing diagram ac electrical characteristics ? - jtag test port timing characteristic sym min typ max units notes 1 tck clock period t tckp 100 ns 2 tck clock pulse width high t tckh 80 ns 3 tck clock pulse width low t tckl 80 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 60 ns 8 tdo output delay t tdod 30 ns c l =30pf 9trst pulse width t trstw 200 ns t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes b 214440 1 26june03
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes:
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